Avinash Reddy

Software Engineer

Bangalore Urban, Karnataka, India7 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Extensive experience in ASIC DDRSS functional verification.
Proficient in all phases of verification from planning to silicon bringup.
Strong communication skills and teamwork capabilities.

Stackforce AI infers this person is a SoC Design Verification Engineer with expertise in ASIC and DFT methodologies.

Contact

Skills

Core Skills

Soc Design VerificationDdr ProtocolDft

Other Skills

SoC verification environmentVerification planningCoverage closureSilicon bringupATPG SimulationAsynchronous reset hazards detectionCVerilogSystem VerilogC++LinuxMatlabProteusTCLAutomatic Test Pattern Generation (ATPG)

About

I have an extensive work experience of several years in ASIC DDRSS functional verification at SOC through all the phases- from Verification planning to Coverage closure and silicon bring up. I hold graduate degree from IIIT Allahabad. Good communication skills along with ability to perform independently as well as in a team environment for technical support

Experience

7 yrs 10 mos

Total Experience

3 yrs 11 mos

Average Tenure

4 yrs 2 mos

Current Experience

Nvidia

Senior Design Verification Engineer

Mar 2022 – Present · 4 yrs 2 mos · Bengaluru, Karnataka, India

Qualcomm

3 roles

Senior Engineer

Promoted

Nov 2021 – Mar 2022 · 4 mos

I am working as Soc Design Verification engineer in the DDR team at Qualcomm. I have worked through all the phases- from Verification planning to Coverage closure and silicon bringup. I have a good understanding over DDR protocol and Soc verification environment.

DDR protocolSoC verification environmentVerification planningCoverage closureSilicon bringupSoC Design Verification

Engineer

Promoted

Nov 2019 – Nov 2021 · 2 yrs

I am working as Soc Design Verification engineer in the DDR team at Qualcomm. I have worked through all the phases- from Verification planning to Coverage closure and silicon bringup. I have a good understanding over DDR protocol and Soc verification environment

DDR protocolSoC verification environmentVerification planningCoverage closureSilicon bringupSoC Design Verification

Associate Engineer

Jul 2018 – Nov 2019 · 1 yr 4 mos

Nxp semiconductors

Internship

Jan 2018 – Jun 2018 · 5 mos · Noida Area, India

Done Internship as DFT engineer in NXP semiconductors, Noida.
Worked on ATPG Simulation and asynchronous reset hazards detection flow.

ATPG SimulationAsynchronous reset hazards detectionDFT

Mentor graphics

Training

May 2017 – Jun 2017 · 1 mo · Bengaluru Area, India

Participated in the Verification of Electronic Design and Systems using System Verilog training program-2017 held by Mentor Graphics, Banglore as a part of Higher Education Program (HEP) initiative