Vaishali A V

Product Engineer

Bengaluru, Karnataka, India6 yrs 4 mos experience

AI EnabledAI ML Practitioner

Key Highlights

Expert in Automatic Test Pattern Generation (ATPG) and DFT methodologies.
Proficient in Python and AI/ML model applications.
Experienced in scan insertion and compression techniques.

Stackforce AI infers this person is a DFT Engineer specializing in VLSI testing and verification.

Contact

Skills

Core Skills

Automatic Test Pattern Generation (atpg)

Other Skills

EDTATPG FaultsAI MLScan insertion and Scan CompressionMBISTVerilogLinuxPython (Programming Language)Joint Test Action Group (JTAG)TetramaxSynopsys toolsBSD compilerVCSSystemVerilogDFT

Experience

6 yrs 4 mos

Total Experience

1 yr 6 mos

Average Tenure

Current Experience

Mediatek

DFT Engineer

Jun 2022 – Jun 2024 · 2 yrs · Bengaluru, Karnataka, India · On-site

Worked in Mediatek as a contractor through Xeliumtech Solutions.

Automatic Test Pattern Generation (ATPG)EDT

Mirafra technologies

DFT Trainer

Oct 2021 – Jun 2022 · 8 mos · Bangalore Urban, Karnataka, India

ATPG FaultsAutomatic Test Pattern Generation (ATPG)

Chipedge technologies pvt ltd

DFT Trainee

Jun 2021 – Oct 2021 · 4 mos · Bangalore Urban, Karnataka, India

Trained in DFT: Scan insertion, Scan Compression, ATPG using Synopsys Tetramax tools (28nm).

Global academy of technology

2 roles

Lecturer, Electronics & Communication

Jul 2008 – Dec 2010 · 2 yrs 5 mos

Lecturer

Jul 2008 – Dec 2010 · 2 yrs 5 mos

Yellamma dasappa institute of technology

Lecturer, Electronics & Communication

Apr 2007 – Jul 2008 · 1 yr 3 mos · Bangalore

Education

Dayananda Sagar Institutions

M.Tech — VLSI and Embedded Systems

Jan 2018 – Dec 2020

Kalpataru Institute of Technology, TIPTUR

Bachelor of Engineering — Electronics & Communication Engineering

Oct 2000 – Jun 2004

JSS College for Women, Chamarajanagar

PUE — PCMB

Jan 1998 – Jan 2000

JSS Girls High School, Chamarajanagar

SSLC

Jan 1997 – Jan 1998

Stackforce found 100+ more professionals with Automatic Test Pattern Generation (atpg)

Explore similar profiles based on matching skills and experience

Tulasi A

Senior DFT Engineer

at Synopsys Inc

Bengaluru, India6 yrs 6 mos exp

DFTASIC

Khushali Dudhagara

Staff DFT engineer

at MediaTek

Bengaluru, India10 yrs 6 mos exp

Vishwa Patel

DFT Engineer

at MediaTek

Bengaluru, India5 yrs 3 mos exp

DFTUniversal Verification Methodology (UVM)

Ram Bahakar

Senior Engineer

at MediaTek

Bengaluru, India2 yrs 10 mos exp

DFTStatic Timing Analysis

Sujay Jain

Senior DFT Engineer

at MediaTek

Bengaluru, India3 yrs 8 mos exp

DFTApplication-Specific Integrated Circuits (ASIC)

RUCHIKA PARATE

Sr. DFt Engineer

at eInfochips (An Arrow Company)

Bengaluru, India6 yrs 5 mos exp

SimulationSpyglass DFT for RTL

LAKSHAY MADAAN

Engineer

at Qualcomm

Uttarakhand, India7 yrs 1 mo exp

ElectronicsField-Programmable Gate Arrays (FPGA)

Jhansi Nallapati

SMTS -- Silicon design engineer

at AMD

Hyderabad, India13 yrs 8 mos exp

DFT architecture planningSilicon Validation