Noshna Yamini Durga Bankina

Software Engineer

Bengaluru, Karnataka, India1 yr 9 mos experience

Key Highlights

  • Expert in formal verification methodologies.
  • Proficient in SystemVerilog and UVM.
  • Experience in IP/SOC verification projects.
Stackforce AI infers this person is a Formal Verification Engineer specializing in semiconductor design and verification.

Contact

LinkedIn

Skills

Core Skills

Formal FundamentalsSystem Verilog

Other Skills

Digital ElectronicsAPB protocolAssertionsLogic buildingVHDLVerilogObject-Oriented Programming (OOP)IP VerificationUniversal Verification Methodology (UVM)SystemVerilog and UVM testbenchLeadership

Experience

1 yr 9 mos
Total Experience
9 mos
Average Tenure
1 mo
Current Experience

Digicomm semiconductor

Formal Verification Engineer

Mar 2026 – Present · 1 mo · Bengaluru, Karnataka, India

Meta for work

Formal Verification Engineer at Meta (CW)

May 2025 – Jul 2025 · 2 mos · Banglore · On-site

  • Worked on FPV for the debug counter and event generation blocks

Samsung semiconductor

Formal Verification Engineer at Samsung (CW)

Dec 2024 – May 2025 · 5 mos · Bengaluru, Karnataka, India · On-site

  • FPV, CDC, VCF, AMBA(APB,AXI3)

Metavlsi

Formal Verification Engineer

Jun 2024 – Jul 2025 · 1 yr 1 mo · Bengaluru, Karnataka, India

  • Formal Verification of IP/SOC
Formal FundamentalsSystem verilog

Chip edge technologies private limited

Trained fresher

Jun 2023 – Jan 2024 · 7 mos · Bengaluru, Karnataka, India

Digital ElectronicsAPB protocol

Education

Mekapati Rajamohan Reddy Institute of Technology and Science

Bachelor's degree — Electrical and Electronics Engineering

Jul 2019 – Apr 2023

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