K

KrishnaPrasad Motamarri

CTO

Bengaluru, Karnataka, India21 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 16 years of experience in VLSI Physical Design and Verification.
  • Expert in leading physical verification activities for communication chips.
  • Proficient in automating regression tests for device-level verification.
Stackforce AI infers this person is a VLSI Physical Design and Verification expert in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Physical DesignVlsiPhysical Verification

Other Skills

ASICTiming closureICSoCVerilogPrimetimeStatic Timing AnalysisdrclvsdfmBiCMOSPlace & RouteCTSEDADRC

About

16 years of experience in VLSI  Physical Design and Verification ( NL to GDS).

Experience

21 yrs 6 mos
Total Experience
5 yrs 4 mos
Average Tenure
13 yrs 1 mo
Current Experience

Qualcomm

Sr Staff Eng/Manager

Apr 2013 – Present · 13 yrs 1 mo · Bengaluru, Karnataka, India

Physical DesignASICVLSIPhysical VerificationTiming closureIC+4

Amd

MTS

Feb 2008 – Apr 2013 · 5 yrs 2 mos

Mentor graphics

CAE

Oct 2007 – Feb 2008 · 4 mos

  • India-CAE for Mentor's calibre products like drc/lvs/drv/rve and dfm
drclvsdfm

Conexant

Lead Design Engineer

Nov 2004 – Oct 2007 · 2 yrs 11 mos

  • leading physical verification activities for communication chips
  • involved in taping out multiple chips at various process nodes
Physical Verification

Tejas networks

Intern

May 2004 – Jul 2004 · 2 mos

  • under summer internship program (after 1st year of my M.Tech), i was part of STM16 device level regression team. and automated some of the regression tests as part of my work.

Education

International Institute of Information Technology Hyderabad (IIITH)

M.Tech — VLSI

Jan 2003 – Jan 2005

Jawaharlal Nehru Technological University

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