Swasti Shah — CTO
• Working experience for extracting the design features and developing the testplan. • Experience in development of test-bench from scratch in SV (System Verilog)/UVM(Universal Verification Methodology) based environment and C++ based environment to do block level functional verification. • Hands on experience in debugging testbench and design related issues. • Develop constraint-based sequence generators, self-checkers, and assertions to verify different test-cases. • Experience in analyzing functional/code coverage and resolved the holes in coverage. • Expertise in regression failure debugging. • Protocol knowledge of APB (Advanced Peripheral Bus), PCS (Physical Coding Sublayer), FLEXE(Flexible Ethernet), GMP (Generic Mapping Procedure), BMP (Bit-Synchronous Mapping Procedure), HDLC (High Level Data Link Control ) and GFP(Generic Framing Processing) protocol knowledge.
Stackforce AI infers this person is a skilled ASIC Verification Engineer with expertise in functional verification and design methodologies.
Location: Ahmedabad, Gujarat, India
Experience: 9 yrs 3 mos
Skills
- Functional Verification
- System Verilog
Career Highlights
- Expert in functional verification and debugging.
- Proficient in System Verilog and UVM methodologies.
- Strong background in protocol analysis and coverage.
Work Experience
Swasau Technology Private Limited
Technical Lead (10 mos)
NVIDIA
ASIC Verification Engineer (4 yrs 5 mos)
eInfochips (An Arrow Company)
Design Verification Engineer (3 yrs 6 mos)
Engineering Trainee (6 mos)
eiTRA - eInfochips Training & Research Academy Ltd
ASIC Trainee (5 mos)
Oizom
Research And Development Intern (1 mo)
Education
B.Tech at Ahmedabad University
High School at Sheth C. N. Vidyalaya
