Kavyashree U S — Product Manager

Physical design engineer with expertise in the whole flow of ASIC design and implementation from Synthesis to PNR , block level STA timing closure and backend checks. Have worked on multiple tapeouts of multimillion gate design in 22nm, 14nm ,10nm and 7nm process nodes.

Stackforce AI infers this person is a VLSI design expert with a focus on ASIC development and physical design.

Location: Bengaluru, Karnataka, India

Experience: 6 yrs 8 mos