Raj Sekhar Bochkar

CEO

India21 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC Physical Design and Methodology.
Proven track record in Timing Closure and Low Power Design.
Leadership in GPU/APU project flow implementation.

Stackforce AI infers this person is a Semiconductor Design Expert with a focus on Physical Design and Timing Closure.

Contact

Skills

Core Skills

Physical DesignTiming Closure

Other Skills

Full chip Floor-planningBus PlanningRepeater InsertionTop level Place & RouteClock Tree SynthesisRoutingPhysical verification signoffStatic Timing AnalysisSignal IntegrityDFTECO flowsPhysical VerificationFloorplanningPower AnalysisPlace & Route

About

Flow Czar for PD flow Strong Hands-on with Signoff Power Analysis Flow Exposure to Low Power Designing and Optimization Hands-on with Physical Designing Strong Shell Scripting and Programming skills Specialties: ASIC Physical Design, Methodology and Flow development, Timing closure, Floorplanning, Clock tree synthesis, Low Power Design closure, IR Drop analysis/closure

Experience

21 yrs 6 mos

Total Experience

5 yrs 4 mos

Average Tenure

10 yrs

Current Experience

Synopsys inc

3 roles

Senior Group Manager

Promoted

Nov 2021 – Present · 4 yrs 6 mos

Solutions Architect

Jun 2019 – Oct 2021 · 2 yrs 4 mos

Senior Member of Consulting Staff

Mar 2016 – May 2019 · 3 yrs 2 mos

Key responsibilities include Driving benchmarks, Technology Proliferation on current & new Technology nodes, Support successful design implementation with Synopsys Physical-Design products
Engagement with Synopsys Customers in Pre-Sales deployment of Physical design tools that includes Hierarchical Design flow, UPF methodologies, Block-Level implementation

Amd

3 roles

Member of Technical Staff

Jul 2012 – Feb 2016 · 3 yrs 7 mos

 Technical Lead working with teams of SoC Integration, IP owners, Synthesis, Place & Route and other local/remote teams
 Hands-on with Full chip Floor-planning, Bus Planning, Repeater Insertion
 Hands-on with Top level (SoC) Place & Route, CTS, Routing and Physical verification signoff
 Responsible for Full chip Static Timing Analysis & Timing Closure of High Performance GPU/APU SoCs
 Handled Multi-clock designs with a frequency over and above 1GHz
 Flow Czar – Lead for flow settings, implementation and roll-out for GPU/APU projects
 Closure of Full chip Signal, DRVs and ECO (Base/Metal) flows
 DFP Signoff using UPFs
 Signoff Physical Verification (DRC, LVS, ERC, DFM) and Tapeout Quality checks
 Expertise across wide spectrum of EDA tools from Synopsys, Cadence, Mentor Graphics, Sierra Pinnacle

Full chip Floor-planningBus PlanningRepeater InsertionTop level Place & RouteClock Tree SynthesisRouting+8

Senior Design Engineer

Promoted

May 2010 – Jul 2012 · 2 yrs 2 mos

ASIC Design Engineer II

Dec 2007 – Apr 2010 · 2 yrs 4 mos

Advanced Micro Devices (NYSE: AMD) is an innovative technology company dedicated to collaborating with customers and technology partners to ignite the next generation of computing and graphics solutions at work, home and play. For more information, visit http://www.amd.com

Cadence

Member of Technical Staff

Mar 2005 – Nov 2007 · 2 yrs 8 mos

 Ownership of Low Power Features like Power Shut-Off (PSO), Power Switch Optimization during Implementation and Signoff, Common Power Format (CPF) support
 New Feature Handling related to Signoff Power Analysis tools like vstorm2, Powermeter, Libgen and validation of Encounter-VSTORM interface
 Gap Closure on Customer designs
 Deploy new Testcases based on Customer Bugs, New Features onto Regression suite
 Ownership of Regressions for new releases
 Ownership of Infrastructure Development and Maintenance