Rajveer Singh

Software Engineer

Lucknow, Uttar Pradesh, India3 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in GPU verification and architecture.
Proven track record in memory controller development.
Hands-on experience in ASIC design and verification.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with a focus on ASIC and GPU technologies.

Contact

Skills

Core Skills

Gpu VerificationMemory ProtocolsAsic Design

Other Skills

Graphics Processing UnitLPDDRVerilogApplication-Specific Integrated Circuits (ASIC)MIPS Instruction SetDDR PHY InterfaceRTL CodingUniversal Verification Methodology (UVM)Synopsys Design CompilerLINTAXISystemVerilogDigital IC DesignC (Programming Language)Xilinx Vivado

About

An innovative career in VLSI design which involves creativity, challenges and provides me opportunity to enhance my knowledge along with technical skills as well as wants to contribute in the growth of organization

Experience

3 yrs 9 mos

Total Experience

1 yr 9 mos

Average Tenure

2 mos

Current Experience

Qualcomm

Senior Engineer (GPU DV)

Mar 2026 – Present · 1 mo · Noida · On-site

Learning GPU architecture and applying verification expertise for signing of the same.

Graphics Processing UnitGPU Verification

Synopsys inc

Senior R&D Engineer

Jan 2023 – Mar 2026 · 3 yrs 2 mos · New Delhi · On-site

Developed and verified DFI LPDDR5, LPDDR6, DDR5 RDIMM, MRDIMM Memory controller and PHY Monitor VIP components.
Analyzed and resolved complex functional failures in subsystem VIPs, contributing to improved regression stability, complete coverage.
Provided technical support to external customers assisting with the design, integration and verification of custom IP
implementations.

LPDDRVerilogMemory Protocols

Mediatek

2 roles

RTL Design Engineer

Jul 2022 – Jan 2023 · 6 mos

Working as RTL design engineer for AXI / AHB protocol based IPs. Familiar with Integration flows such as LINT, PA, PTPX etc Hands on experience for tools such as Verdi, Design compiler etc. Also involved in basic Verification such as coverage, exclusion review of AHB / AXI Based IPs.

Application-Specific Integrated Circuits (ASIC)VerilogASIC Design

Intern

Aug 2021 – Jul 2022 · 11 mos

Worked on Design, Verification and Synthesis of one small block inside 5G Modem. Learnt about 5G Air interface, OFDM , Resource Grid concepts and implemented one Resource mapper block successfully

Application-Specific Integrated Circuits (ASIC)MIPS Instruction SetASIC Design