Chandra B V — Software Engineer
Experience in ASIC Synthesis , Physical design, Signoff STA, LEC, PV, RV. Expertise: Physical aware synthesis using Synopsis Fusion Compiler. Physical Design using ICC2, FC. Timing analysis using Synopsis Prime time. Logical Equivalence Check using LEC , FM. Hardware Description Languages : Verilog. Scripting languages : Perl, TCL, UNIX Shell Scripting.
Stackforce AI infers this person is a Physical Design Engineer with expertise in ASIC design and verification.
Experience: 8 yrs
Skills
- Physical Design
- Timing Analysis
- Asic Synthesis
- Signoff Sta
Career Highlights
- Expert in Physical Design and ASIC Synthesis.
- Proficient in using Synopsys and Cadence tools.
- Strong background in timing analysis and logical equivalence checks.
Work Experience
AMD
Physical Design Engineer (3 yrs 9 mos)
Intel Corporation
Physical Design Engineer (3 yrs 8 mos)
Qualcomm
Synthesis and STA Engineer (7 mos)
MediaTek
Physical Design Engineer (10 mos)
Education
Master’s Degree at Vellore Institute of Technology
Bachelor of Engineering - BE at JSSATE Bangalore
PCMB at Rural college, Kanakapura-561117
at Jain Vidyaniketan
