Nruthya Rajagopal — Product Engineer
Skills • ASIC flow (RTL TO GDS) • RTL design and simulation using Verilog. • Logic synthesis. • Physical design-Placement and routing, Physical Verification Specialties: embedded systems, FPGA, Knowledge of Logic design, ASIC flow, special interests in Static Timing analysis and Physical design Tools • Cadence tool suite: Innovus • Synopsis tool suite: Design compiler, VCS, Prime Time, IC compiler I/II • Mentor Graphics tool suite: Calibre DRC, LVS,
Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC and Physical Design.
Location: Bangalore Urban, Karnataka, India
Experience: 10 yrs 9 mos
Skills
- Physical Design
- Power Integrity
Career Highlights
- Expert in Physical Design and Power Integrity.
- Proficient in ASIC flow from RTL to GDS.
- Strong background in embedded systems and FPGA design.
Work Experience
MediaTek
Physical Design Engineer (4 yrs)
Nanyang Technological University
Research Associate (6 mos)
GLOBALFOUNDRIES
Senior Design Enablement Engineer (3 yrs 9 mos)
Aztecsoft Ltd
Test Engineer (2 yrs)
Sansera Engineering Pvt Ltd
Graduate Apprentice (6 mos)
Education
Master's degree at Nanyang Technological University Singapore
Advance Diploma at RV-VLSI Design Center
BE at VTU
