Suman Tanwar

Software Engineer

Bengaluru, Karnataka, India14 yrs 6 mos experience

Highly Stable

Key Highlights

Over 9 years of experience in VLSI-DFT.
Expertise in Scan Insertion and ATPG methodologies.
Proven track record at leading tech companies.

Stackforce AI infers this person is a VLSI-DFT expert in the Semiconductor industry.

Contact

Skills

Core Skills

DftAtpgDfdMbist

Other Skills

ScanAutomatic Test Pattern Generation (ATPG)SimulationsSpyglassDebuggingVerilogProject ManagementEmbedded SystemsTestingMicrosoft OfficeRequirements AnalysisUnixMicrocontrollersProgramming

About

Results-driven VLSI-DFT professional with a B.Tech in Electronics and Telecommunication and over 9 years of dedicated experience in VLSI. Expertise includes Scan Insertion, ATPG, MBIST, and Fault Simulation. Adept at collaborating with cross-functional teams, mentoring, and implementing DFT methodologies. Proven track record at AMD, Intel, and other leading organizations, having worked on complex chip-level DFT architecture.

Experience

14 yrs 6 mos

Total Experience

2 yrs

Average Tenure

2 yrs

Current Experience

Qualcomm

Staff Engineer - DFT

May 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

Amd

Senior DFT Engineer

Nov 2020 – Nov 2023 · 3 yrs · Bengaluru South, Karnataka, India · On-site

Complete ownership of 15 plus blocks.
Scan Insertion, TPI, wrappers, compression, DRC, scannability and sanity checks.
ATPG pattern generation for SAF, TDF and CA with SDC, debugging low coverage.
Simulation with and without timing, debugging simulation failures.
Collaboration with cross-functional teams and CAD team.
Training on DFT and AMD flows.
Mentoring juniors and interns.

ScanAutomatic Test Pattern Generation (ATPG)SimulationsDFTATPG

Intel corporation

SoC Design Engineer

Oct 2018 – Oct 2020 · 2 yrs · Bangalore · On-site

Worked on Intel in-house DFD components.
RTL DFD integration for SoC, Code reviews, Caliber checks.
Pattern translation.

DFTDFD

Altran

Advanced Engineer

Dec 2016 – Sep 2018 · 1 yr 9 mos · Bangalore

Ownership of 12 plus blocks.
ATPG pattern generation, simulation, coverage analysis, pattern translation.
MBIST at block level and top level using PMBIST, pattern generation, simulations.
Debugging issues for MBIST as PMBIST was used for the first time in the project.
Training others on PMBIST flow.

DFTAutomatic Test Pattern Generation (ATPG)MBISTSimulationsATPG

Hcl technologies

DFT Engineer

Aug 2015 – Nov 2016 · 1 yr 3 mos · Bengaluru Area, India

SPYGLASS DRC checks, MBIST insertion and simulations.
Scan insertion, ATPG pattern generation and simulations.

DFTScanMBISTAutomatic Test Pattern Generation (ATPG)SpyglassSimulations+1

L&t technology services limited

Sr. Engineer

Oct 2011 – Oct 2014 · 3 yrs · India

Experience in Mobile Testing and Embedded Development.
Developing test suite, writing testcases, Reviewing test cases, Risk analysis.
Testing of Mobile applications, Escape defect analysis, PR verification.
Sanity Testing, Expert Testing, Regression Testing.
Logging issues and interacting with developer.
Experience on various mobile platforms – Iden, GB, ICS , JB.
Designing hardware for embedded circuits.
Programming microcontrollers.
Analysis and debugging of the circuits.

Wipro technologies

Project Engineer

Jan 2010 – Jul 2011 · 1 yr 6 mos · Bengaluru Area, India

Experience includes VLSI-DFT on Unix/Linux platform - Fault Modeling, Fault Simulation, Vector generation for stuck-at, Transition faults.
Vector Simulation.
Mapping Block level vectors to Top level.
Coverage, VGR analysis and improvement.
Memory BIST, Debugging.
Basic Knowledge in LBIST, Boundary Scan, RTL coding using Verilog, gate/ RTL level simulation.