Kathyayini YR — Software Engineer
Stackforce AI infers this person is a verification engineer specializing in digital electronics and FPGA design.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 9 mos
Skills
- Digital Electronics
- Verilog
Career Highlights
- Experienced in digital electronics and verification methodologies.
- Proficient in Verilog and System Verilog for design verification.
- Strong background in FPGA design and implementation.
Work Experience
NVIDIA
Senior Verification Engineer (1 yr 5 mos)
AMD
Senior silicon design engineer (9 mos)
Silicon Design Engineer 2 (2 yrs 6 mos)
Contractor (2 yrs)
SmartSoC Solutions Pvt Ltd
Verification Engineer (2 yrs 2 mos)
Education
professional development course at Sandeepani School of VLSI Design
Bachelor of Engineering - BE at Govt. S K S J Technological Institute, BANGALORE
