Jul 2011 – Jan 2019 · 7 yrs 6 mos · Greater Hyderabad Area

• Work involves
• Block and full chip physical verification activities. Handled several tapeouts for multi-million gate chips by running Physical Verification checks such as DRC, LVS, ERC, Antenna, DFM for 28nm and 20nm nodes
• Block level netlist-to-gds flow including floorplanning, placement, CTS, routing and STA using Synopsys and Cadence tools
• GNB (Graphics North Bridge) chip-tile implementation. Worked on channel implementation between the blocks, resolving block interface DRC’s, pin misalignments, power grid editing and routing
• Full chip RDL generation and feedback implementation from IR team to resolve IR drop issues
• Resolving block level low power multi-voltage design issues using Verdi Signoff-LP

Jul 2007 – Jul 2011 · 4 yrs · Greater Hyderabad Area

• Work involved
• Block and full chip physical verification activities. Handled several tapeouts for multi-million gate chips by running Physical Verification checks such as DRC, LVS, ERC, Antenna, DFM for 150nm to 45nm nodes
• Development and optimization of standard cell libraries suiting various project requirements using Virtuoso Layout Migrate tool. Created low-leakage, high-density and high-speed std cell libraries at 90 and 65nm technologies.
• Modifying existing 65nm libraries to increase yield by incorporating DFM.
• Design of special cells such as power management cells (Header cells, always-on buffer, state-retention flip-flops), negative edge triggered flip-flops, programmable delay cells.
• Characterization and select back-end view creation.
• Verifying all the libraries before release using Flow-QA.
• Evaluating performance of all libraries by using them in benchmark circuits such as ARM processor. This benchmarking is done using P&R tools.
• Memory Characterization. Characterized numerous Artisan and VirageLogic (now Synopsys) memories used in various projects using Legend memory characterization tool

Mar 2006 – Aug 2006 · 5 mos · Vermont, USA

• Work involved development of specialized programs to aid in Microchip production
• Wrote Tcl/Tk scripts for aiding in the process of reviewing potential defects found in OPC (Optical Proximity Correction) Verification. The script, which is integrated with the Calibre tool, automates several process steps and creates web pages for easy display and convenient storage of results. This script is currently in routine production use