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Beemarjun Reddy Kallem

Software Engineer

Hyderabad, Telangana, India3 yrs 5 mos experience

Key Highlights

  • 3 years of experience in Synthesis and STA.
  • Hands-on expertise in Physical design and ASIC flow.
  • Proficient in multiple EDA tools and programming languages.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Static Timing Analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing AnalysisAsic Design

Other Skills

Synopsys IC CompilerSynopsys PrimetimeSynopsys Fusion CompilerCLPConformal LECTCLPerlLinuxPython (Programming Language)Verilog

About

Synthesis & STA Engineer with around 3 years of experience.Currently part of Integration team responsible for performing Physical aware synthesis,LEC,CLP and STA.

Experience

3 yrs 5 mos
Total Experience
2 yrs 10 mos
Average Tenure
7 mos
Current Experience

Cadence design systems (india) pvt. ltd.

Design Engineer II

Oct 2025 – Present · 7 mos · Hyderabad, Telangana, India

Mediatek

Synthesis and STA Engineer

Nov 2022 – Sep 2025 · 2 yrs 10 mos · Bengaluru, Karnataka, India

Rv-vlsi vlsi and embedded systems design center

Physical design Trainee

Apr 2022 – Nov 2022 · 7 mos · Bengaluru, Karnataka, India

  • Hands-on experience with Synopsys ICC2 and PrimeTime.
  • Gained knowledge of ASIC flow from RTL to GDSII.
  • Expertise in PNR tasks like Floorplan, powerplan, Placement,CTS and Routing.
  • Worked on Designing a block at 40nm technology.
  • Understood the basic STA concepts and CMOS logic design.
  • Worked on clean up of DRC,LVS and Antenna violations.
Synopsys IC CompilerSynopsys PrimetimePhysical DesignStatic Timing Analysis

Education

CVR College of Engineering, Hyderabad

Bachelor of Technology - BTech — Electronics and communication engineering

Jan 2017 – Jan 2021

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