Anshumesh S.

Product Engineer

Bengaluru, Karnataka, India0 mo experience

Key Highlights

Experienced in Physical Design Engineering at Intel.
Proficient in Embedded Systems and Circuit Design.
Strong background in ASIC Design Verification.

Stackforce AI infers this person is a Semiconductor and Electronics Engineering specialist with a focus on ASIC design and embedded systems.

Contact

Skills

Core Skills

Physical Design EngineeringAsic DesignEmbedded SystemsCircuit DesignAsic Design VerificationRtl Design

Other Skills

Tcl-TkSynopsys Fusion CompilerFunctional TestingVerilogPerlC++LinuxSynopsys VCSSynopsys VerdiArduino IDEESP8266Embedded Software ProgrammingEmbedded CMicrocontrollerEmbedded Software

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Intel

Physical Design Engineering Intern

May 2025 – Apr 2026 · 11 mos · Bengaluru, Karnataka, India · On-site

Worked on the physical design of the family level of IP, which involves integrating the common lane and data lanes at an advanced technology node using the tool Synopsys Fusion Compiler.
Executed the APR FC Flow from reading the RTL design to the generation of the GDSII file at the family level of IP.
Performed signoff flows, such as logical equivalence checks and layout verification, at the family level of IP.

Tcl-TkSynopsys Fusion CompilerPhysical Design EngineeringASIC Design

Indian institute of technology, bombay

Internship

Oct 2023 – Dec 2023 · 2 mos · Mumbai, Maharashtra, India · On-site

Worked on testing of Embedded System Kits having Arduino UNO
microcontroller and various sensors.
Worked on the designing of the Circuit and Layout of the PCB for Embedded Systems.

Embedded SystemsFunctional TestingCircuit Design

Synopsys inc

Intern

Aug 2022 – Aug 2023 · 1 yr · Hyderabad, Telangana, India · On-site

Worked in ASIC design verification of interoperability between the controller IP UFSHC and IP M-PHY.
Debugged the RTL design, having a combination of the controller IP UFSHC, with IP M-PHY at advanced technology nodes.
Worked closely with architecture and RTL designers to develop a comprehensive verification plan based on IP core standard specifications.
Executed power-aware verification with both modes, UPF and Non-UPF.

VerilogPerlASIC Design VerificationRTL Design