Aug 2020 – Dec 2024 · 4 yrs 4 mos · Hyderabad, Telangana, India

• Worked on MI300 till Mi450 series critical symmid pair tiles.
• TSMC 5nm down to 2nm FinFET hands on work experience.
• Handled critical timing and power metric issues.
• Power budget achievement challenges.
• Crossfunctional teams collaboration.

May 2018 – Jun 2020 · 2 yrs 1 mo · Penang, Malaysia · On-site

• Responsible for delivering ECO project with tight time schedules.
• Handled Crital Timing tiles.
• Intel 10nm FinFET technology,
• Tools : Cadence INNOVUS,Primetime, Mentor : Calibre

Jun 2014 – May 2018 · 3 yrs 11 mos · Hyderabad Area, India · On-site

• Resonsabilities: complete PNR flow from floorplan to GDS-II
• Handled critical tiles interms of timing, power, area, IR critical tiles
• Lead a team and guided them to close the tiles in time.
• Resolved congestion on rectilinear tiles with diffrerent floorplans and blockages.
• Worked on ECO projects and delevered them intime.
• Worked on Analog layouts , PLL and its testchip tapeouts.
• Technology: TSMC 16nm,14nm,7nm,5nm. GF 14LPP, GF 22fdsoi
• Tools: Synopsis ICC,ICC2,Fusion compiler, Prime-Time, StarRC, cadence virtuoso, caliber DRC,LVS.