Tanay M. — Director of Engineering
Engineering Manager at Intel India with ~10 years of experience in Physical Design/timing convergence, involved in multiple tape outs of intel integrated & Discrete (client/gaming and AI/Datacenter) GPUs. I was part of SD backend execution team delivering high performance L2/L3 cache blocks for three different generations of intel client/discrete GPUs. Have worked on physical design execution of various blocks of video encoders/decoders: Media sub-system, color/Z/FF: graphics 3D cluster, L2/L3 cache & memory fabric subsystems across multiple generations of intel integrated GPUs and discrete GPUs (client/gaming & AI/datacenter HPC GPU) , Have exposure of working on HBM memory controller PNR execution on the SoC side. Currently leading SoC Peripherals subsystem PNR execution efforts right from the Floor planning to synthesis, PNR till Sign-off for next generation AI accelerator.
Stackforce AI infers this person is a Semiconductor Design Engineer specializing in AI GPU architecture and physical design.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs
Skills
- Physical Design
- Soc Design
Career Highlights
- Led PNR execution for next-gen AI accelerator.
- Delivered high-performance cache blocks for Intel GPUs.
- Expert in physical design and timing convergence.
Work Experience
Intel Corporation
Physical Design Engineering Manager (10 yrs 7 mos)
STMicroelectronics
Internship (5 mos)
Education
Master of Technology - MTech at Vellore Institute of Technology
Bachelor of Engineering (B.E.) at North Maharashtra University
