Sanjay V — Software Engineer
• Comprehensive knowledge on ASIC Flow. • Understanding on various challenges involved in maintaining DRC and LVS. • Working knowledge on Physical Implementation of design from Netlist to GDSII. • Effective placement of high macro count during Floor planning based on Data Flow and Powerplan management at an estimated IR drop. • Implementing timing driven Placement and removal of Congestion hotspots. • Static Timing Analysis and the concepts of OCV, AOCV, MCMM, CRPR. • Analyze scan paths and fix issues post Synthesis using TMAX for DRC and coverage check. • Knowledge on CLP. • In depth knowledge on MOS theory, Transistor theory. • Scripts: Tcl, Perl. • EDA Tools: Synopsys ICC, PrimeTime, TetraMax. • Familiar OS: Windows and LINUX.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and VLSI technologies.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 8 mos
Skills
- Application-specific Integrated Circuits (asic)
- Static Timing Analysis
- Synthesis
- Timing Closure
Career Highlights
- Expert in ASIC Flow and Physical Design.
- Proficient in Static Timing Analysis and DRC.
- Experienced in high macro count placement strategies.
Work Experience
Samsung Semiconductor
Staff Engineer (2 mos)
MediaTek
Senior Engineer (4 yrs 1 mo)
Engineer (2 yrs 5 mos)
Education
Post Graduate Diploma in Physical Design at RV VLSI Design Centre
Bachelor of Engineering (B.E.) at JSS Academy Of Technical Education Karnataka
PCME at SBMJC
SSLC at Auden Institute of Education
Middle School at SSVM
