Sanchit Kulkarni

Product Engineer

Bengaluru, Karnataka, India2 yrs 8 mos experience

Key Highlights

Expert in backend SOC chip design.
Proficient in 3nm, 5nm, and 7nm technologies.
Developed scripts to enhance design efficiency.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and SoC development.

Contact

Skills

Core Skills

Physical DesignSilicon DesignEmbedded Systems

Other Skills

Fusion compilerTiming ClosureTCLPythonSynopsys PrimeTimeSynopsys Fusion CompilerC++Real-time Control SystemsLinuxEngineeringPhysical VerificationICCFlow support PnrBackend VlsiShell Scripting

About

Working on the backend side of SOC chip design. Currently working on the 3nm technology. Have worked on high frequency 5nm and 7nm technology IPs from complete floorplanning to place and route. I believe I have strong technical and scripting knowledge, helping me to do challenging tasks. Also contributed a lot of complex scripts to AMD making the process faster and efficient. I’m the best at what I do.

Experience

2 yrs 8 mos

Total Experience

2 yrs 5 mos

Average Tenure

3 mos

Current Experience

Google

Silicon Physical Design

Feb 2026 – Present · 3 mos · Bengaluru, Karnataka, India

Working on next generation TPUs

Physical DesignSilicon Design

Amd

3 roles

Senior Silicon Design Engineer

Dec 2025 – Feb 2026 · 2 mos

Silicon Design Engineer 2

Jul 2023 – Dec 2025 · 2 yrs 5 mos

> Owned SoC blocks in 3nm & 5nm nodes from floorplanning through Placement, CTS, Routing, ECO implementation &
signoff, delivering high-frequency, timing and congestion-critical designs to successful tapeouts.
> Provided Flow support for different Design-For-Power flows like Multi-Voltage, Low-power (Power gated) and Always-
On flavors by debugging and providing quick fixes/workarounds to the team.
> Experience in converging Multivoltage, Always-on and Power gated blocks by resolving MV-timing through multi-mode
multi-corner (MMMC) analysis, solving DRC/LVS challenges across advanced nodes.
> Delivered a tapeout-ready SoC block having multiple PHY interfaces which were timing and DRC critical. Created scripts
for pin extension, port placement, and density screens, accelerating block closure and ensuring a smooth sign-off.
> SCRIPTS & AUTOMATION:
Developed several scripts for AMD helping the team to converge design faster:
Synopsys PrimeTime based tcl script to fix final setup and hold violations during ECO phase.
Synopsys Fusion-Compiler based tcl script to fix data transition, clock transition, glitches reducing manual efforts.
Fusion-Compiler based script to fix shorts and DRC violations helping the team and improving convergence speed.
Flow integrated scripts: Clock based LPICG swaps, Buffering Analog macro pins, dumping floorplan for 3nm node &
dumping utilization reports at every stage.
Tcl script to fix timing using skewing, helping in identifying useful skew for the block owner.
Developed a Python-based script to extract SoC-wide timing, latency, utilization, and congestion metrics, of all
blocks providing a comprehensive overview of each block and enabling faster, data-driven design convergence.
> Collaborated with RTL, STA, DFT, and power teams to resolve timing, test, and power intent issues for SoC blocks.

Fusion compilerTiming ClosurePhysical DesignSilicon Design

Physical Design Intern

Jan 2023 – Jun 2023 · 5 mos

> Trained on 7nm block-level physical design flows, gaining hands-on experience in place-and-route (PNR), timing closure,
and signoff procedures.
> Developed a Python-based script to generate block-level summaries at each PD stage and automatically creating
PowerPoint presentation with all key block metrics for reviews.

Physical DesignFusion compiler