Pradeep Bhat

Director of Engineering

Bengaluru, Karnataka, India22 yrs 1 mo experience

Highly Stable

Key Highlights

Expert in Design-for-Test technologies
Led teams delivering ASIC/DFT solutions
Proven track record in silicon validation

Stackforce AI infers this person is a semiconductor industry expert with a focus on DFT and silicon validation.

Contact

Skills

Core Skills

DftSilicon ValidationDesign-for-testJtagPost-silicon Validation

Other Skills

Project ManagementPeople ManagementSemiconductorsBoundary ScanBISTAutomatic Test Pattern Generation (ATPG)TestingAutomatic Test EquipmentDebuggingVerilogUnix Shell ScriptingShell ScriptingPerlIntegrated Circuit DesignASIC

About

Chip design professional with excellent knowledge of Design-for-Test (DFT) technologies. Leading a team of engineers specialized in full-chip DFT implementation, verification, and post-Si support.

Experience

22 yrs 1 mo

Total Experience

3 yrs 11 mos

Average Tenure

2 yrs 4 mos

Current Experience

Alphawave semi

Director - DFT

Jan 2024 – Present · 2 yrs 4 mos · Bangalore Urban, Karnataka, India

As an Engineering Director (ASIC Design - DFT) at Alphawave Semi, I am responsible for managing a team of engineers and overseeing DFT feature implementation on all Custom Silicon business Unit projects. With more than 10 projects executed in parallel, I am dedicated to deploying industry-leading ASIC testability features and ensuring that we meet schedule and quality goals.
In my role, I lead my team and collaborate with key stakeholders to deliver top-notch ASIC/DFT solutions tailored to meet the unique needs of each customer. I am also involved in team hiring and training, setting priorities and schedules, vendor management, and handling customer escalations.
The effectiveness of my team and our commitment to customer satisfaction are at the forefront of everything we do. I am proud to lead a team that consistently delivers exceptional results and exceeds expectations.

DFTSilicon ValidationProject ManagementPeople ManagementSemiconductorsBoundary Scan+16

Amd

Senior Manager - DFX

Mar 2019 – Dec 2023 · 4 yrs 9 mos · Bangalore

Managing a team of ~20 Design-For-Test Engineers.
My team is responsible for defining Full-Chip level DFX feature goals, execution milestones, DFX-RTL integration from IP to SoC environment, Verification of ATPG, MBIST, JTAG, loopback and other features, ATE pattern delivery and post-Si support.

DFTDesign-For-TestDFXATPGMBISTJTAG+2

Nvidia

2 roles

Manager - DFT

Apr 2016 – Mar 2019 · 2 yrs 11 mos

High speed interfaces such as GDDRx, HBM, PCIE, USB operate at multi Gbps speeds and have components not covered by traditional ATPG/MBIST. I have led a team of ~10 engineers and provided end-to-end manufacturing test coverage (BIST) for these components on all Nvidia Products.

DFTBISTJTAGHigh-speed interfacesManufacturing test coverage

Senior DFT Engineer

Jul 2007 – Apr 2016 · 8 yrs 9 mos

Expert in DFT flows targeted at High-Speed Interface BIST, JTAG/IEEE1500, HBM test, MBIST, Scan/ATPG implementation. I was involved in DFT insertion, verification and silicon characterization/debug on ATE.

DFTHigh-Speed Interface BISTJTAGMBISTScan/ATPG implementation