RUSTUM PRASAD SAHU

Software Engineer

Bengaluru, Karnataka, India11 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 5 years of experience in VLSI industry
  • Expertise in DDR IO design and SRAM circuits
  • Proficient in advanced CMOS technology nodes
Stackforce AI infers this person is a VLSI design engineer with expertise in semiconductor technologies.

Contact

Skills

Core Skills

SemiconductorsClock DistributionHigh Speed SerdesSram Design

Other Skills

DDR IO designTiming analysisEMIR simulationsPower simulationsCharacterizationMicrosoft OfficeMatlabPowerPointWindowsMicrosoft ExcelMicrosoft WordAutoCADTeamworkCVerilog

About

• Offering 5 years of experience in VLSI industry. • currently working in DDR IO design. • Experience of working on SRAM Memory circuits, High speed Serdes, Clock circuits. • Profound knowledge of cmos circuits fundamentals and worked on 14nm, 7nm technology nodes. • Consistent learner, enthusiastic to further enhance my knowledge.

Experience

11 yrs 4 mos
Total Experience
2 yrs 10 mos
Average Tenure
7 yrs 10 mos
Current Experience

Samsung r&d institute india - bangalore private limited

Staff Engineer

Jul 2018Present · 7 yrs 10 mos · India

  • working in different DDR IO standards circuit design.
DDR IO designSemiconductors

Amd

Design Engineer (consultant from si2chip)

Aug 2016Jun 2018 · 1 yr 10 mos · Bengaluru Area, India

  • Design of clockspine (H-tree/V-tree + Mesh buffer) for distribution of different clocks in MPU/GPU.
  • Based on Prime Time results to match the skew at each level.
Clock distributionTiming analysis

Globalfoundries

analog mixed signal engineer (Consultant from si2chip)

May 2015Jul 2016 · 1 yr 2 mos · Bengaluru Area, India

  • Complete understanding of High speed SerDes Transmitter circuit.
  • Running schematic, RC extracted timing sims for different Tx macros and organize, analyze the
  • results and to do improvement in circuits to meet the timing specifications.
  • Running the EMIR simulations, Power simulations. Worked to resolve EMIR violations with
  • layout people.
High speed SerDesEMIR simulationsPower simulations

Si2chip technologies pvt. ltd.

Associate Design Engineer

Oct 2014Apr 2015 · 6 mos · Bengaluru Area, India

  • Design and Characterization of SRAM 64x8_MUX4.
  • Characterization of memory margins, timings.
SRAM designCharacterization

Education

Indian Institute of Technology, Kharagpur

Master of Technology (M.Tech.) — Microelectronic & VLSI Design

Jan 2012Jan 2014

Chhattisgarh Swami Vivekanand Technical University, Bhilai

Bachelor of Engineering (BE) — Electronics and Communication Engineering

Jan 2008Jan 2012

Shri Mahavir Jain Higher Sec. School

12th

Jan 2007Jan 2008

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