Anup Korde

Software Engineer

Bengaluru, Karnataka, India15 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in STA and Physical Verification methodologies.
  • Proven track record in automating design verification processes.
  • Strong collaboration skills across multiple engineering teams.
Stackforce AI infers this person is a Semiconductor Engineering Expert with a focus on Physical Design and Verification.

Contact

Skills

Core Skills

Sta/timingPhysical Verification

Other Skills

Design Rule Checking (DRC)Clock DistributionEDAPhysical DesignTCLPythonPython (Programming Language)Floorplanning

Experience

15 yrs 3 mos
Total Experience
5 yrs 1 mo
Average Tenure
11 yrs 11 mos
Current Experience

Intel corporation

Staff Engineer | Signoff [STA/Timing, Physical Verification (PDV)]

Jun 2014Present · 11 yrs 11 mos · Bengaluru · On-site

  • STA/Timing:
  • Define, develop, and deploy industry leading STA and ECO methodologies across multiple design teams.
  • Drive continuous innovation in timing flows, improving runtime, accuracy, and overall execution efficiency.
  • Own end to end STA methodology, from constraints development to timing closure sign off.
  • Collaborate closely with PNR, RTL, Extraction, and Technology teams to ensure smooth convergence at both block and top levels.
  • Tackle complex timing challenges on advanced nodes.
  • Physical Verification:
  • Develop, maintain, and optimize Physical Design Verification (PDV) flows and runsets
  • Automate and support physical verification flow for internal design tools group
  • Support tape-out and design-related foundry interface activities, physical verification CAD flow, and CAD flows for SOC integration
  • Develop and maintain validation procedures for physical verification flow and prepare user guides and documents and review results and create validation test cases
  • Design Rule Check (DRC) analysis and resolution
  • Layout vs. Schematic (LVS) verification,Electrical Rule Check (ERC) validation
  • Antenna and density rule verification, Advanced process node verification (7nm/5nm/3nm)
  • Block-level and SoC-level Layout vs. Schematic (LVS) verification
  • Design Rule Checks (DRC) debugging and resolution
  • Delta Voltage DRC issues analysis and correction
  • Density violations troubleshooting and optimization
  • Engineering Change Order (ECO) phase verification support
STA/TimingPhysical VerificationDesign Rule Checking (DRC)Clock DistributionEDAPhysical Design+2

Synopsys

Corporate Application Engineer

Aug 2013May 2014 · 9 mos · Hyderabad Area, India

  • Physical Design
Physical Design

Cadence

Senior Member of Technical Staff

Jan 2011Sep 2013 · 2 yrs 8 mos · Noida, Uttar Pradesh, India

Education

Birla Institute of Technology and Science, Pilani

Master of Technology — MicroElectronics

Yeshwantrao Chavan College of Engineering - YCCE

Bachelor's degree — Electrical and Electronics Engineering

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