Jun 2014 – Present · 11 yrs 11 mos · Bengaluru · On-site

• STA/Timing:
• Define, develop, and deploy industry leading STA and ECO methodologies across multiple design teams.
• Drive continuous innovation in timing flows, improving runtime, accuracy, and overall execution efficiency.
• Own end to end STA methodology, from constraints development to timing closure sign off.
• Collaborate closely with PNR, RTL, Extraction, and Technology teams to ensure smooth convergence at both block and top levels.
• Tackle complex timing challenges on advanced nodes.
• Physical Verification:
• Develop, maintain, and optimize Physical Design Verification (PDV) flows and runsets
• Automate and support physical verification flow for internal design tools group
• Support tape-out and design-related foundry interface activities, physical verification CAD flow, and CAD flows for SOC integration
• Develop and maintain validation procedures for physical verification flow and prepare user guides and documents and review results and create validation test cases
• Design Rule Check (DRC) analysis and resolution
• Layout vs. Schematic (LVS) verification,Electrical Rule Check (ERC) validation
• Antenna and density rule verification, Advanced process node verification (7nm/5nm/3nm)
• Block-level and SoC-level Layout vs. Schematic (LVS) verification
• Design Rule Checks (DRC) debugging and resolution
• Delta Voltage DRC issues analysis and correction
• Density violations troubleshooting and optimization
• Engineering Change Order (ECO) phase verification support