Sanjay Shinde

Director of Engineering

Bengaluru, Karnataka, India28 yrs 7 mos experience

Most Likely To Switch

Key Highlights

Expert in Timing Closure and Low Power Design.
Proven leadership in Silicon Design Engineering.
Extensive experience in ASIC and VLSI projects.

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in ASIC and VLSI engineering.

Contact

Skills

Core Skills

Timing ClosureDesignPhysical DesignRtl DesignChip LeadPerformance

Other Skills

Low PowerDFTPowerAreaSoCSemiconductorsStatic Timing AnalysisPrimetimeASICICLogic SynthesisFunctional VerificationVLSIFormal VerificationVerilog

About

Specialties: Timing Closure Design Low Power

Experience

28 yrs 7 mos

Total Experience

2 yrs 2 mos

Average Tenure

2 yrs 3 mos

Current Experience

Amd

Director Silicon Design Engineering.

Feb 2024 – Present · 2 yrs 3 mos · Bengaluru, Karnataka, India · On-site

Timing ClosureDesignLow Power

Intel corporation

Director / SOC Design Manager (Intel Automotive)

Nov 2021 – Feb 2024 · 2 yrs 3 mos · Bengaluru, Karnataka, India

Micron technology

ASIC Design Director 3DXP ENGG

Apr 2020 – Nov 2021 · 1 yr 7 mos · Bengaluru, Karnataka

Cientra (formerly mindlance technologies)

AVP

Jun 2018 – Mar 2020 · 1 yr 9 mos · Bangalore

Mindlance technologies

AVP

Feb 2017 – Jun 2018 · 1 yr 4 mos · Bengaluru Area, India

Aricent

Director Technology SES

Jul 2016 – Jan 2017 · 6 mos · Bangalore

Broadcom limited

ASIC Manager

Aug 2015 – May 2016 · 9 mos · Allentown, Pennsylvania Area

Lsi corporation

2 roles

ASIC Manager

Jan 2014 – Aug 2015 · 1 yr 7 mos · Bangalore

SOC Lead

Oct 2011 – Dec 2013 · 2 yrs 2 mos · Bangalore

Infosys technologies limited.

Lead Consultant.

Mar 2011 – Oct 2011 · 7 mos

Lead teams of Physical design, DFT and RTL Design.
Recruitement from campus and latrel hiring.
Mentor team of engineers on Design, DFT and Physical design ramp up.
Lead one account (tier 1 semiconductor company) for all design services.
Leading-n-mentoring a team of 9 engineers for design closure.

Physical DesignDFTRTL Design

Pmc-sierra

Lead Design Engineer

Jan 2008 – Mar 2011 · 3 yrs 2 mos

Chip Lead for Next Gen SAS Raid on Chip.
Product details @ http://www.pmc-sierra.com/products/details/pm8020
1st SOC done at India design centre.
Complete ownership & coordination with various teams in North America.
Hire and ramp-up engineers for deisign funtionality and flows-n-methodologies.
Drive Performance, Power, Area, along with test coverage.
Coordinate IP handoffs, tracking the schedule & quality.
Define clock-domain-crossover check flow.
Drive synthesis recipies and track area-n-power at all stages of the design cycle.
Drive floorplan with pad-ring for die-size reduction.
Discuss spec. requireents with Architect to achive faster closure.
Drive all audit discussions to closure.
IP Lead (Memory sub-subsystem)
Enhance the older design for higher bandwidth, lower latency.
Define microarchitecture in coordination with chip arhitect and FW architects.
Publish Spec. for all the teams to ensure the integration is smooth.