Pamulapati Abhinav

Software Engineer

Guntur, Andhra Pradesh, India4 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced RTL Design Engineer with strong digital design skills.
  • Proficient in SystemVerilog and Verilog for complex designs.
  • Hands-on experience with CDC and Lint methodologies.
Stackforce AI infers this person is a Digital Design Engineer with expertise in RTL design and verification.

Contact

LinkedIn

Skills

Core Skills

Digital DesignsRtl Coding

Other Skills

CDCLintSystemVerilogVerilogCatalog ManagementFev ConformalSystem on a Chip (SoC)Digital LogicIP integrationUniversal Verification Methodology (UVM)APB ProtocolAXI ProtocolSPI ProtocolLinuxQuestaSim

Experience

4 yrs 8 mos
Total Experience
4 yrs 7 mos
Average Tenure
4 yrs 8 mos
Current Experience

Intel corporation

Design Engineer

Oct 2021 – Present · 4 yrs 7 mos · Bengaluru, Karnataka, India

CDCLintDigital DesignsRTL Coding

Hcl technologies

Design Engineer

Sep 2021 – Present · 4 yrs 8 mos · Bangalore Urban, Karnataka, India

SystemVerilogVerilogDigital DesignsRTL Coding

Vlsiguru training institute

Design Verification Engineer

Mar 2021 – Sep 2021 · 6 mos · Andhra Pradesh, India

SystemVerilogVerilogDigital DesignsRTL Coding

Education

Vignan's Lara Institute of Technology and Science, Vadlamudi, Chebrolu Mandal, PIN-522213(CC-FE)

Bachelor of Technology - BTech

Jan 2016 – Sep 2020

Stackforce found 100+ more professionals with Digital Designs & Rtl Coding

Explore similar profiles based on matching skills and experience

SA

Swetha A.

Graphics Hardware Engineer (IP design)

at Intel Corporation

Bengaluru, India7 yrs exp
Interconnect/Fabric DesignD2D DesignSoC DesignNetwork on-chip Design
Abhay Kumar Mishra

Abhay Kumar Mishra

Senior Staff Engineer

at Synopsys Inc

Noida, India13 yrs 1 mo exp
SystemVerilogUniversal Verification Methodology (UVM)
Abhishek Patel

Abhishek Patel

SoC Design Engineer

at Intel Corporation

Thanesar, India2 yrs 3 mos exp
RTL DesignStatic Timing Analysis
UK

Ujjwal Kant

ASIC Emulation Engineer

at Intel Corporation

Austin, United States11 yrs 10 mos exp
Saurin Shah

Saurin Shah

Staff Engineer

at Qualcomm

Bengaluru, India12 yrs 1 mo exp
Physical DesignPlace & Route
RK

Raushan kumar

Synthesis and STA Engineer

at LanceSoft, Inc.

Bengaluru, India1 yr 7 mos exp
Logic SynthesisStatic Timing Analysis
Anuj Srivastava

Anuj Srivastava

Senior Design Manager

at Google

Bengaluru, India14 yrs 5 mos exp
Farheen Safdar

Farheen Safdar

Physical Design Engineer

at Google

Bengaluru, India1 yr 10 mos exp
Physical DesignVery-Large-Scale Integration (VLSI)Python (Programming Language)