Gokulnath P

Director of Engineering

India10 yrs 1 mo experience

Highly Stable

Key Highlights

Expert in Design for Testability (DFT) methodologies.
Proven track record in SoC design and validation.
Strong scripting skills for automation in DFT processes.

Stackforce AI infers this person is a DFT expert in semiconductor design and validation.

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Skills

Core Skills

Design For TestabilityDftSoc DesignDesign VerificationScan Design

Other Skills

Test timing constraints managementDFT implementationValidation closuresScan frontend implementationLV-MBISTDFT insertionCoverage analysisSimulationsScan implementationAutomated scriptsTest timing constraintsScan architecture definitionYield loss diagnosisFunctional Gate level SimulationARM Integration Design Verification

Experience

10 yrs 1 mo

Total Experience

4 yrs 1 mo

Average Tenure

1 yr 10 mos

Current Experience

Intel corporation

Logic Design Engineering Manager

Jul 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India · Hybrid

Test timing constraints management for a SoC.
Enabling fish tail for constraint generation and validations at RTL level for the quick turnaround.
Leading the Media IP level DFT implementation and validation closures.
Scan frontend implementation and test timing constraints ownership for the Media IP.

Test timing constraints managementDFT implementationValidation closuresScan frontend implementationDesign for testabilityDFT

Qualcomm

Lead Senior Engineer

Jan 2022 – Jun 2024 · 2 yrs 5 mos · Greater Chennai Area · On-site

LV-MBIST and core level DFT insertion, coverage analysis and simulations.
Sub system level complete DFT ownership.
Top level scan implementation for a SoC.
Analyzing the spyglass based DFT and atspeed reports.
Handling the scan ecos through automated scripts in DC/PnR tools.
Providing test timing constraints for SoC and reviewing the timing reports.
SaF pattern generation and simulations/validations at SoC level, debugging coverage gaps if any.
Analyzing the functional and test clock matrix through spyglass

LV-MBISTDFT insertionCoverage analysisSimulationsScan implementationAutomated scripts+3

Analog devices

3 roles

Senior Design Engineer

Promoted

Apr 2020 – Dec 2021 · 1 yr 8 mos

Defining Scan architecture from specification to implementation.
Field return/yield loss scan diagnosis to root cause the issue.
Functional Gate level Simulation.
ARM - A55 Integration Design Verification.

Scan architecture definitionYield loss diagnosisFunctional Gate level SimulationARM Integration Design VerificationDesign verificationDFT

Design Engineer

Aug 2016 – Apr 2020 · 3 yrs 8 mos

Responsible for scan DFT implementations throughout the project timeline.
DFT-DRC violations fix in the RTL through spyglass dft.
Scan coverage analysis.
Scan insertion during synthesis.
Setting up of ATPG and simulation flow with gate level netlists.
Debugging zero delay and timing issues in scan GLS.
Debugging atpg/simulation mismatch.
Scan mode (shift/stuckat/atspeed constraints) static timing analysis.
Power estimation of peak scan activity patterns.
Silicon scan failure diagnostics and debug.
JTAG boundary scan design and verification.
SoC design integration and automating integration through script.
Proficient in scripting languages - Shell/Perl
Design quality checks and analysis - LINT/CDC/DFT runs.

Scan DFT implementationsDFT-DRC violations fixScan coverage analysisATPG setupDebuggingJTAG boundary scan design+2

Student Intern

Jan 2016 – Jul 2016 · 6 mos

Worked in the verification of DSP hardware accelerators in an SoC.
Understood the working of FIR/IIR/FFT accelerators in the Digital Signal Processing chip.
Developed the perl model for these accelerators(FIR/IIR/FFT) which quickly completed the DV process.
Verified the stability of the MAC units with randomly generated 32 bit single precision, 40 bit extended precision, 64 bit double precision floating point inputs and fixed point inputs against the perl reference model with some acceptable tolerance.
Constrained the inputs and verified Infinity, NaN, Overflow and Underflow floating point outputs.
During the process, developed a strong knowledge in SHARC assembly language and written a test conversion and generation script in perl to verify the new features of the accelerators.
Performance verification of the improved hardware accelerators.

Verification of DSP hardwarePerl model developmentFIR/IIR/FFT acceleratorsTest conversion and generation