Zuhair Ahmed Khan — Software Engineer
• SRAM Circuit Design (6T-Bitcell), Register File Design (8T-Bitcell) in 2nm and 3nm technology • Vector & Measurement implementation in N2SRF. • Timing Analysis: Setup, Hold, Cycle Time, Access Time • Marginality Qualification (Read Margin. Write Margins. Functional internal hold margins) • Timing, Power and Leakage Analysis & Characterization using FineSim. • Bitcell analysis, ,Sense amplifier analysis, Critical Path Tight Stimuli(CPTS) • Read & Write Assist techniques • Statistical analysis using monte-carlo & solido simulations. • Mixed-Signal layout design in 3nm, 4nm & 7nm Finfet technologies (TSMC and Samsung Foundry) • Good handle in UNIX and Shell Scripting • Tools: FineSim, Primesim, Calibre, WaveView, Cadence Virtuoso, Solido
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Memory Circuit Design.
Location: New Delhi, Delhi, India
Experience: 4 yrs 3 mos
Skills
- Memory Circuit Design
- Analog Layout Design
Career Highlights
- Expert in SRAM and Register File Circuit Design.
- Proficient in Mixed-Signal Layout Design across multiple technologies.
- Strong background in Timing and Power Analysis.
Work Experience
Intel Corporation
Digital Circuit Design Engineer (8 mos)
Mirafra Technologies
Design Engineer II | Memory Circuit Design (1 yr 9 mos)
Broadcom
Memory Circuit Design (Contractor) (1 yr 9 mos)
Qualcomm
Analog Layout Design Engineer (Consultant) (7 mos)
Zia Semiconductor Pvt Ltd
Design Engineer I | Analog Layout Design | Memory Circuit Design (1 yr 10 mos)
InMovidu Technologies Pvt Limited
Embedded System (2 mos)
Education
Bachelor of Technology - BTech at Jamia Millia Islamia
Intermediate at Aligarh Muslim University
High School (10th) at Ayesha Tarin Modern Public School , Aligarh
