J

jagadeesh reddy

Software Engineer

Bengaluru, Karnataka, India9 yrs 3 mos experience
Highly Stable

Key Highlights

  • Expert in Physical Design and Methodology Development.
  • Proven track record in design automation and verification.
  • Strong debugging skills with a focus on design flow issues.
Stackforce AI infers this person is a Physical Design Engineer with expertise in VLSI and CAD methodologies.

Contact

Skills

Core Skills

Physical DesignMethodology Development

Other Skills

Design AutomationPhysical VerificationProject ManagementStrategic PlanningAnalog layout designStatic timing analysisICC Compiler.tclVery-Large-Scale Integration (VLSI)Design Rule Checking (DRC)matlabECOSemiconductorsLayout Versus Schematic (LVS)verilog

About

• Successfully deployed/supported TFM to multiple projects across severs, graphics, client business groups inside the organization. • Lead as design expert for the projects and worked as the key support for tape-in from methodology team. • Worked on methodology of PnR flow from Netlist to GDSII for the faster convergence of the designs for the incremental changes in the technology nodes. • Worked on implementing/designing sanity checks required for the various stages of the design. • Worked with clocking team and handled the challenges with respect to the recent methodologies in CTS. • Worked on signoff aware PnR implementation with respect to IR, EM, Thermal, LV. • Good knowledge on Congestion techniques and routing techniques on digital blocks. • Excellent debugging skills to root cause the issues in the design/flow. Find solutions through work arounds and scripts till tool fixes/solutions are available. • Partnered with global CAD team in developing and deploying advanced node flows to meet quick TAT and better PPA. • Supported backend design automation flows as per the backend implementation team requirement (on-site & off-site) across the globe. • Converging designs with better QoR and delivering executive summary to the designers. • Communicating with technology department to define design rules and later translate them into an accurate runsets. • Layout Verification lead engineer and TFM owner for multiple server & client projects. • Development and maintenance of Physical Verification flows through multiple vendor tools – Calibre, ICV. • Defining the specifications of the various custom physical verification runsets based on the project need basis. • Worked on Support/Automation requests by the Designers. • Supported the flow issues on LVS, density flows, High Voltage rules verifications, Reliability verifications which includes Latch up, Electrostatic discharge (ESD), Antenna.

Experience

9 yrs 3 mos
Total Experience
9 yrs 3 mos
Average Tenure
9 yrs 3 mos
Current Experience

Intel corporation

2 roles

Senior Methodology Engineer

Promoted

Jul 2018Present · 7 yrs 9 mos

Physical DesignMethodology DevelopmentDesign AutomationPhysical Verification

Physical Design Engineer

Jan 2017Jul 2018 · 1 yr 6 mos

Education

National Institute of Technology Karnataka

PG

Jawaharlal Nehru Technological University college of Engineering, Anantapur

B.Tech — Electrical and Electronics Engineering

BIE

Intermediate (+2) — Maths Physics

Khadri High school

SSC

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