Naveen D

Software Engineer

Bengaluru, Karnataka, India5 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in UVM-based verification methodologies.
Proven experience in VLSI design and verification.
Strong background in low-power design techniques.

Stackforce AI infers this person is a VLSI and Verification Engineer with expertise in digital design and verification methodologies.

Contact

Skills

Core Skills

Silicon DesignSystem On A Chip (soc)VerificationUvmDigital Video Broadcasting

Other Skills

C++APB protocolDVB-SHFunctional VerificationUniversal Verification Methodology (UVM)DFTJoint Test Action Group (JTAG)JtagDesign PatternsSilicon ValidationATEAvfsEMCCLDOFirmware

About

I am a highly organized, detail oriented, enthusiastic, fast learner, self-starter, flexible, reliable, efficient in fast-paced multitasking environments. I am seeking a position of responsibilities that utilizes my skills and experience in the organization that offers professional growth while being creative, flexible and resourceful. ➦ Technical Summary ➳ 11 months Project Trainee at ANURAG LABS,DRDO Hyderabad. ➳ Pursued M.E(ES&VLSI Design) from CBIT ,Osmania university Hyderabad ➳ Skills in building UVM based SystemVerilog test-benches from scratch. ➳ DVB-SH,AMBA AHB APB Verification IP development Experience. ➦ Field of Interest ➳ VLSI - RTL Design, IP Verification ➳ Verification - Constrained random verification, Coverage driven verification, Functional/Protocol verification. ➳ Protocols - AMBA-AHB,APB. ➦ Technical Skills HDLs ➜ Verilog HVL ➜ SystemVerilog Verification Methodology ➜ UVM Protocols ➜ AMBA - AHB,APB, ETHERNET Scripting Language ➜ perl EDA Tool ➜ ncsim, Xilinx ISE, Modelsim Language ➜C OS ➜ Linux, Windows Skills ➜ Functional Verification, Constrained-random Verification, Coverage Analysis

Experience

5 yrs 10 mos

Total Experience

1 yr 11 mos

Average Tenure

4 yrs 9 mos

Current Experience

Amd

Sr. Silicon Design Engineer

Aug 2021 – Present · 4 yrs 9 mos · Bengaluru Area, India

C++System on a Chip (SoC)Silicon Design

Svm micro sysstems.

Trainee

Aug 2015 – Nov 2015 · 3 mos · Hyderabad Area, India

"Designing a verification Environment to the APB protocol using UVM”
Description: The project involves designing a verification environment , connecting a master and slave agents through an interface without using an DUT.
Tool: http://www.edaplayground.com/x/NXd

UVMAPB protocolVerification

Advanced numerical research and analysis group (anurag) ,drdo.

Verification of a Digital Video Broadcoasting -Satellite services to Handheld Devices(DVB_SH) IP.

Sep 2014 – Jul 2015 · 10 mos · Hyderabad Area, India

The project involves verification of an intellectual property known as a Digital Video Broadcoasting -Satellite services to Handheld Devices(DVB_SH) IP using UVM verification Methodology.DVB-SH is the name of a mobile broadcast standard,designed to deliver video ,audio and data services to small handheld and vehicle mounted devices.
Responsibilities :
Verification plan
Designing a different verification components and interfacing them.
verifying a Design with better coverage report.

UVMDVB-SHVerificationDigital Video Broadcasting

Synopsys compiler tool

Hybrid Encoded Booth Multiplier with RSA Technique (RSAT).

Jan 2011 – Apr 2011 · 3 mos · Shastra Micro systems,Hyderabad,india

"Hybrid Encoded Booth Multiplier (HEBM) with Reduced Switching Activity Technique (RSAT)."
Role : Analyzer and Developer.
Team size : 3
Duration : 90 Days
Description: A low power Hybrid Encoded Booth Multiplier (HEBM) with Reduced Switching Activity Technique (RSAT) for DSP functions that encounter a wide diversity of operating scenarios in battery powered low power wireless sensor network system. This RSAT approach has been applied on the hybrid encoder of the multiplier to reduce the power consumption. The hybrid encoder in the low power multiplier uses both the Booth and proposed technique. If the number of 1's less than or equal to three the proposed encoding technique used otherwise go for Booth technique. The switching activity of the proposed multiplier has been reduced when compared with conventional and Booth multiplier respectively. It is observed from the Verilog DC Tool power report that the power consumption of the proposed multiplier has been reduced when compared with conventional and Booth multiplier.