Rajesh S

Director of Engineering

Bengaluru, Karnataka, India17 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and VLSI technologies.
Proven leadership in managing engineering teams.
Extensive experience in ASIC design and verification.

Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in physical design engineering.

Contact

Skills

Core Skills

Physical DesignVlsiAsic

Other Skills

Clock Tree SynthesisPhysical VerificationCadenceStatic Timing AnalysisIntegrated Circuit DesignTiming ClosureTop Level Physical DesignIO PlanningBump PlanningPhysical Design VerificationLECIR-Drop analysisFloor planningP&REM/IR Drop Analysis

About

A person who likes to take challenging tasks by working on cutting edge technologies and keep myself updated to benefit self and the organization I am working for.

Experience

17 yrs 3 mos

Total Experience

2 yrs 10 mos

Average Tenure

4 yrs 5 mos

Current Experience

Intel corporation

SoC Physical Design Technical Lead & Engineering Manager

Dec 2021 – Present · 4 yrs 5 mos · Bengaluru, Karnataka, India

Physical DesignVLSIASICClock Tree SynthesisPhysical VerificationCadence+3

Cadence design systems

Principal Product Engineer

Jun 2020 – Nov 2021 · 1 yr 5 mos · Bengaluru, Karnataka, India

Ampere

Senior Staff Design Engineer

Apr 2018 – Jun 2020 · 2 yrs 2 mos · India

Appliedmicro

Staff Design Engineer

Jun 2015 – Mar 2018 · 2 yrs 9 mos · Bengaluru Area, India

Open-silicon

2 roles

Lead Engineer

Jan 2015 – May 2015 · 4 mos

Lead ASIC Design Engineer responsible for Top Level Physical Design activies, IO Planning, Bump Planning, Partition of Blocks, Timing Closure and Physical Design Verification.

Top Level Physical DesignIO PlanningBump PlanningTiming ClosurePhysical Design VerificationPhysical Design+1

Senior ASIC Design Engineer

Oct 2011 – Dec 2014 · 3 yrs 2 mos

Physical Design Engineer responsible for timing closure, LEC, IR-Drop analysis and Physical Verification activities in Block level

Timing ClosureLECIR-Drop analysisPhysical VerificationPhysical DesignVLSI

Wipro limited

2 roles

Senior Physical Design Engineer

Apr 2010 – Sep 2011 · 1 yr 5 mos · Cochin Area, India

ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc
Hands on experience and expertise in Cadence

Floor planningClock Tree SynthesisP&REM/IR Drop AnalysisSignal Integrity closureLow power implementation+2

Physical Design Engineer

Aug 2008 – Mar 2010 · 1 yr 7 mos · Cochin Area, India

ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc
Hands on experience and expertise in Cadence

Floor planningClock Tree SynthesisP&REM/IR Drop AnalysisSignal Integrity closureLow power implementation+2