Bhagyashree Kinagi

Software Engineer

Bangalore, Karnataka, India7 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expert in Full Chip Layout and Physical Verification.
  • Strong background in ESD planning and signoff.
  • Proficient in advanced semiconductor design tools.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and physical verification.

Contact

LinkedIn

Skills

Core Skills

Full Chip LayoutPhysical VerificationRdlEm

Other Skills

IRESDRedhawkRHSCFusion CompilerBump planningMIMCapTCLShell ScriptingSoC Power Delivery and ReliabilityLayout DesignPlacement and Routing (PNR)Application-Specific Integrated Circuits (ASIC)TeamworkSynopsys IC Compiler

About

EMIR signoff | ESD planning and signoff | MIM | PTPX | Power Estimation | RDL and bump plannjng | Full chip layout convergence | Physical Verification.

Experience

7 yrs 9 mos
Total Experience
6 yrs 1 mo
Average Tenure
1 yr 8 mos
Current Experience

Amd

Sr. Silicon Design Engineer

Sep 2024 – Present · 1 yr 8 mos · Bengaluru, Karnataka, India · Hybrid

IREMESDRedhawkRHSCFusion Compiler+13

Intel corporation

SoC Design Engineer

Jul 2018 – Aug 2024 · 6 yrs 1 mo · Bengaluru, Karnataka, India

RDLEM

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — Microelectronics

SDM College of Engg & Tech , Dharwad

Bachelor of Technology — Electronics and Communication

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