Siddesh Halavarthi Math Revana

CEO

Bengaluru, Karnataka, India25 yrs 5 mos experience
Highly Stable

Key Highlights

  • Led a team of 500 engineers in CPU design.
  • Authored articles on advanced verification techniques.
  • Successfully deployed Portable Stimulus Standard.
Stackforce AI infers this person is a Semiconductor industry expert with a focus on CPU design and verification.

Contact

LinkedIn

Skills

Core Skills

Cpu DesignTechnical LeadershipCpu Systems DesignDesign Verification

Other Skills

Performance ModelingU-ArchitectureRTL DesignVerificationCPU Systems ArchitecturePost-Si DebugLow-Power ModesCoherencyDebug ModesSW Use-CasesAssertion Based VerificationFormal VerificationCoverage Convergence TechniquesDDR Memory ControllersHigh-Speed PHYs

About

An experienced VLSI professional with a track record of managing Design and Verification of leading edge Memory Controllers, interconnects and CPU Systems. Proficient in setting and delivering on quality goals and aggressive schedules by deploying state-of-the-art design and verification methodologies and techniques. Has authored articles on Assertion Based Verification, Coverage Convergence and Formal Verification Techniques and presented in international conferences too. Specialties: Technical Leadership with emphasis on Quality & Schedule Design and Verification of CPU & DDR Systems spanning across func, low-power and performance aspects ACE/CHI/AXI/AHB/APBI BUS and LPDDRx/PCDDRx DDR Protocols Constrained Random, Formal Verification and Convergence Techniques Early adoption and successful deployment of Portable Stimulus Standard (PSS) UPF based low-power design and validation of complex systems

Experience

25 yrs 5 mos
Total Experience
11 yrs 9 mos
Average Tenure
1 yr 11 mos
Current Experience

Amd

Corporate Vice President

Jul 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India · On-site

  • CPU Design
  • Leading India Cores team (CPU team), an extremely passionate group of 500 engineers highly focused on delivering industry-leading performance-per-watt CPUs across server, client, and S3 products. Our strength lies in deep expertise across perf modeling, u-arch/RTL, u-arch DV, Performance DV, formal, and cutting-edge PD and GDS delivery. Committed to driving excellence across the development lifecycle and shaping the future of energy-efficient, high-performance computing through trusted partnerships with global teams in Zen core innovations
CPU DesignPerformance ModelingU-ArchitectureRTL DesignVerificationTechnical Leadership

Qualcomm

Sr Dir, Engineering

Jul 2002 – Jul 2024 · 22 yrs · Bengaluru Area, India

  • CPU systems Architecture, Design, Verification and Post-Si debug leadership
  • CPU systems Design and Architecture which involves latest/greatest/high-end CPU cores, clusters, coherent interconnects and bunch of IPs to make the system work. Has "2" granted US patents.
  • Experienced in CPU low-power modes, coherency, debug modes, SW use-cases and Post-Si aspects. Coined and driven impactful CPU initiatives to improve efficiency and quality of deliverables across multiple product lines.
  • Previously worked extensively on core level design verification of leading edge DDR Memory Controllers (LPDDR1/2/3/4 and PCDDR2/3), high-speed PHYs, cross-bars and network interconnects (NoC), integrated verification of interconnect+Memory controllers+PHY, NAND-Flash, MIPI-LCD, NOR-Flash. Has a little exposure to Modem Core design and verification as well.
  • Has taken initiatives to successfully deploy Assertion Based Verification, Formal Verification and Coverage Convergence Techniques.
CPU Systems ArchitectureDesign VerificationPost-Si DebugLow-Power ModesCoherencyDebug Modes+2

Velankani information systems

Design Engineer

Dec 2000 – Jun 2002 · 1 yr 6 mos · Bangalore, India

  • Design and verification of Viterbi Encoder and Decoder for 3G wireless
Design VerificationViterbi EncoderViterbi Decoder

Education

Birla Institute of Technology and Science (BITS), Pilani

Master of Science (MS) — Microelectronics

Bapuji institute of engineering and technology

Bachelor of Engineering — Electronics and Communication

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