Atul Kashyap

Product Engineer

Bengaluru, Karnataka, India22 yrs 8 mos experience
Highly Stable

Key Highlights

  • 20+ years in chip-level power convergence and signoff.
  • Expert in SOC power optimization techniques.
  • Proven leadership in standard cell development.
Stackforce AI infers this person is a Semiconductor Design Expert with a focus on power optimization and standard cell development.

Contact

Skills

Core Skills

SocPower OptimizationStandard Cell DevelopmentLibrary Specification

Other Skills

RTL power optimizationpower estimationLow power designHigh speed designASICSemiconductorsVerilogVLSIVHDLAnalogCMOSICEDAFPGAARM

About

20+ Years of industry experience on Chip level power convergence and signoff focusing on the optimization of design based on different design KPI's, Standard Cell Design , Library PPA and Benchmarking. Having expertise on SOC power optimization techniques , RTL power optimization, PTPX and debugging capabilities. Extensive knowledge on Standard Cell Library development, Architecture definition, Definition of standard cell portfolio , Library Benchmarking. Worked on standard cell development across a vast range of technologies including bulk CMOS (130nm down to 28nm), FDSOI CMOS (28nm, 22nm and 14nm) to FINFET (14nm and 7nm). Excellent People Management and Project Management capabilities. Excellent communication, interpersonal skills and leadership quality along with profound engineering skills.

Experience

22 yrs 8 mos
Total Experience
5 yrs 4 mos
Average Tenure
1 yr 4 mos
Current Experience

Amd

PMTS Silicon Design Engineer

Jan 2025Present · 1 yr 4 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

2 roles

Engineering Manager

Aug 2018Dec 2024 · 6 yrs 4 mos

SOC POWER LEAD

Aug 2018Aug 2020 · 2 yrs

  • Working on different class of SOC's.
  • SOC Power optimization to provide competitive and best in class design.
  • Starting with RTL power optimization, working with Implementation team to ensure best power optimized recipe for Synthesis/Physical Design, power estimation and work to meet/beat the use case power for the SOC.
SoCpower optimizationRTL power optimizationpower estimation

Invecas

Senior Member of Technical Staff

Sep 2015Aug 2018 · 2 yrs 11 mos · Bengaluru Area, India

  • I was leading the Standard cell development across different technology. (22FDSOI, 14FinFet, 7NM)
  • Responsibility include defining the complete specification of different track of library development and concluding the specification with Foundry.
  • Cell set definition for the platform offering.
  • Designing of Low power and high speed flops and combinational logic for different design need.
Standard Cell DevelopmentLibrary SpecificationLow power designHigh speed design

St microelectronics

Manager

Mar 2004Sep 2015 · 11 yrs 6 mos · Noida Area, India

Itm gorakhpur

Lecturer

Aug 2003Mar 2004 · 7 mos

Education

Madan Mohan Malvia Engg College Gorakhpur

BE — Electronics & Communication

Jan 1998Jan 2002

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