Atul Kashyap — Product Engineer
20+ Years of industry experience on Chip level power convergence and signoff focusing on the optimization of design based on different design KPI's, Standard Cell Design , Library PPA and Benchmarking. Having expertise on SOC power optimization techniques , RTL power optimization, PTPX and debugging capabilities. Extensive knowledge on Standard Cell Library development, Architecture definition, Definition of standard cell portfolio , Library Benchmarking. Worked on standard cell development across a vast range of technologies including bulk CMOS (130nm down to 28nm), FDSOI CMOS (28nm, 22nm and 14nm) to FINFET (14nm and 7nm). Excellent People Management and Project Management capabilities. Excellent communication, interpersonal skills and leadership quality along with profound engineering skills.
Stackforce AI infers this person is a Semiconductor Design Expert with a focus on power optimization and standard cell development.
Location: Bengaluru, Karnataka, India
Experience: 22 yrs 8 mos
Skills
- Soc
- Power Optimization
- Standard Cell Development
- Library Specification
Career Highlights
- 20+ years in chip-level power convergence and signoff.
- Expert in SOC power optimization techniques.
- Proven leadership in standard cell development.
Work Experience
AMD
PMTS Silicon Design Engineer (1 yr 4 mos)
Intel Corporation
Engineering Manager (6 yrs 4 mos)
SOC POWER LEAD (2 yrs)
INVECAS
Senior Member of Technical Staff (2 yrs 11 mos)
ST Microelectronics
Manager (11 yrs 6 mos)
ITM Gorakhpur
Lecturer (7 mos)
Education
BE at Madan Mohan Malvia Engg College Gorakhpur