Jun 2016 – Sep 2018 · 2 yrs 3 mos · India

• I belong to IACG (Intel Architecture Core Group) at Intel. This group is responsible for designing next generation Microprocessors that drive Servers, Laptops and Desktops. My team is involved in the design of Microprocessor cores. I work on the design of Functional Unit Blocks (FUBs). A FUB is a floor plannable object that performs a particular function. Each FUB performs particular function such as adding, swapping,decoding. I design datapath FUBs pertaining to ALU and cache memory of the core. As a PDE, I am responsible for the hierarchical circuit design as well as the Layout design of the FUBs. My work involves Floorplanning, hierarchical circuit design, Logic optimization, Scan Chain design, Logic Verification, Layout Design, Timing Closure and Physical Verification.
• The pivotal aspect of my work involves fixing the timing of all the nets that are reported to have timing violations. The timing optimization and fixing is done manually based on the report generated through Static Timing Analysis tool. The Timing of all the nets is verified post fixes by using the same tool. Timing of clock nets and clock paths are optimized and the clock skew is reduced by performing Clock Tree Synthesis and STA plays a vital role obtaining the timing of clock paths. I also design Layout of the FUBs by manually performing placement optimizations taking into consideration the timing and availability of routing resources, and routing all the nets. Routing is performed once the placement is completed. Timing Closure is performed by fixing the timing of nets after they are routed and meeting the desired timing of each routed net. Physical Verification which involves fixing DRCs is performed and Reliability Verification is done and issues such as Electromigration, high IR drop across a logic cell and Self Heat are fixed. In the past 2 years at Intel , I have worked on multiple projects that comprise of 14nm and 10nm core micro-architecture.