Vishal Gore

DevOps Engineer

Bengaluru, Karnataka, India11 yrs 6 mos experience

Highly Stable

Key Highlights

10 years of experience in Analog/RF layout design.
Expertise in technology nodes from 400nm to 6nm.
Proficient in TX-Rx, ADCs, and Power Management ICs.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Analog and RF layout design.

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Skills

Core Skills

Analog LayoutVery-large-scale Integration (vlsi)

Other Skills

Cadence VirtuosoCadence Virtuoso Layout EditorQuality ChecksRF LayoutLayout DesignSemiconductorsElectronicsShell ScriptingRoboticsDigital ElectronicsControl Systems DesignRubyMicrosoft ExcelMicrosoft WordMicrosoft Office

About

10 years of experience in Analog/RF layout design, with technology nodes ranging from 400nm to 6nm. Worked extensively on TX-Rx,ADCs, Power Management ICs. (LDO, Band gap, bias generators, POR, etc)

Experience

11 yrs 6 mos

Total Experience

6 yrs 9 mos

Average Tenure

4 yrs 9 mos

Current Experience

Qualcomm

2 roles

Lead Layout Engineer

Promoted

Dec 2024 – Present · 1 yr 5 mos · On-site

Analog LayoutCadence Virtuoso

Senior Layout Engineer

Sep 2021 – Dec 2024 · 3 yrs 3 mos · On-site

Cadence Virtuoso Layout EditorAnalog Layout

Karmic design private ltd

Analog Layout Design engineer

Dec 2014 – Sep 2021 · 6 yrs 9 mos · Manipal, Karnataka

Experience in Analog layout and memory design, using Cadence Virtuoso and performing Quality Checks like DRC, LVS, Antenna rule checks,etc.
Hands-on experience in module level floorplan & chip level routings. Good understanding of circuit & device functionality which assists in optimised floorplan and critical route plans.

Very-Large-Scale Integration (VLSI)Cadence Virtuoso