PARTHA SARATHI PATRA — Software Engineer
Around 12.5yrs. of total exp. in VLSI ASIC Domain including ASIC Verification, Gate Level Simulation & Post Silicon Validation using various EDA tools.
Stackforce AI infers this person is a VLSI ASIC expert with extensive experience in verification and simulation.
Location: Bengaluru, Karnataka, India
Experience: 13 yrs 4 mos
Skills
- Functional Verification
- Vlsi
- System On A Chip (soc)
- Gate Level Simulation
Career Highlights
- 12.5 years of experience in VLSI ASIC domain.
- Expert in Functional Verification and Gate Level Simulation.
- Proficient in multiple EDA tools and methodologies.
Work Experience
Qualcomm
Staff Engineer (2 yrs 5 mos)
Senior Lead Engineer (3 yrs 7 mos)
Aricent
Lead Engineer (1 yr 9 mos)
Senior Verification Engineer (1 yr 11 mos)
Wipro
Senior Verification Engineer (1 yr 4 mos)
eInfochips
Engineer, ASIC Division (2 yrs 4 mos)
Education
GRADUATION(B.TECH) at Biju Pattnaik University of Technology, Orissa
10th at Town High School Balasore
