Neha Anand

Software Engineer

Bengaluru, Karnataka, India12 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in memory compiler development across multiple foundries.
Proficient in advanced memory design techniques and verification.
Experienced in cutting-edge semiconductor technologies down to 4nm.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in memory layout and compiler development.

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Skills

Core Skills

Memory DesignVerification

Other Skills

memory compiler developmentfloor-planningdesignanalysisquality controlparametric checksECO implementationbitcell swappingdesigns for manufacturingoptimizationSRAM Memory Compiler Layout DesignRow decoder layout1x4 decoder layout developmentLayout development of strapcellsDecoder Top level LVS/DRC

About

Working as Memory Layout Design Engineer. Experience in memory compilers , porting the compiler from one foundry to other and have done leafcell development. Good knowledge of memory design including bitcell, sense amp, decoders and I/O. Worked on Technologies like 4nm, 5nm, 7nm, 10nm,14nm, 28nm, 40nm, 65nm. Verification capabilities includes DRC, LVS, EM/IR, ANTENNA, LEFCHECK, ERC, DFM, DENSITY using Calibre, Hercules. Development of SRAM/REGISTERFILE/ROM memories. Worked with TSMC, SAMSUNG, INTEL and UMC Foundries. EDA tools: Custom Layout Design using CDesigner and Virtuoso Layout editor. Good command on scripting languages like shell.

Experience

12 yrs 3 mos

Total Experience

4 yrs

Average Tenure

7 yrs 10 mos

Current Experience

Qualcomm

2 roles

Lead Layout Engineer

Nov 2022 – Present · 3 yrs 6 mos

Senior Layout Engineer

Jul 2018 – Nov 2022 · 4 yrs 4 mos

Synopsys

Memory Layout Design Engineer

Jan 2015 – Jun 2018 · 3 yrs 5 mos · Noida, Uttar Pradesh, India

Worked on memory compiler development through floor-planning, design, analysis, verification, quality control and other associated parametric checks for foundries (TSMC, INTEL, UMC, GF).
Projects covered :
GF 07 Nanometer HDRF2P Compiler.
TSMC 07 Nanometer ROM Compiler.
INTEL 14 Nanometer UHDRF2P Compiler.
TSMC 16 Nanometer HS1P Compiler.
TSMC 40 Nanometer HDRF1P Compliler.
UMC 28 Nanometer HSRF1P Compiler.
Responsibilities:
Layout Leaf development of different blocks.
Verification and Validation
Product Quality Analysis includes DRC, LVS, EM/IR, ANTENNA, LEFCHECK, ERC, DFM, DENSITY using Calibre, ICV, and HERC.
ECO implementation in layouts and chcells extraction.
Porting (bitcell swapping) for foundry in 28nm and 40nm technology.
Product Realization and Analysis - Designs for Manufacturing and Optimization.

memory compiler developmentfloor-planningdesignanalysisverificationquality control+6

Zia semiconductor pvt ltd

Design Engineer 1

Jan 2014 – Dec 2014 · 11 mos

SPHS SRAM Memory Compiler Layout Design in 40nm
Responsibility:
Row decoder layout.
1x4 decoder layout development.
Layout development of strapcells.
Decoder Top level LVS/DRC.
Array Organizatio with
Edge cells.
Strap cells.
Corner cells.

SRAM Memory Compiler Layout DesignRow decoder layout1x4 decoder layout developmentLayout development of strapcellsDecoder Top level LVS/DRCmemory design