Navneet Kishan — Product Engineer

As a seasoned SoC Design Engineer with over 7 years of experience at Intel Corporation, I bring a wealth of expertise in layout verification (LV), SubFC Integration, Die File Creation, Physical Design and VLSI design. My career has been marked by significant contributions to multiple node technologies, including 7nm, 6nm, 4nm, and 10nm. Technical Expertise: ● Physical Design Verification: Proficient in leading LV analysis and cleanup for complex SoC projects. ● LV/SubFC Integration: Skilled in coordinating SubFC integration and managing die file creation. ● VLSI Design: Experienced in developing novel XSI-based die file flows and optimizing PNR ECO processes. ● Multi-Technology Expertise: Adept at resolving complex issues across various node technologies while collaborating with cross-functional teams. Leadership & Collaboration: ● Team Leadership: Proven track record of training teams on LV flows and managing multiple projects simultaneously. ● Cross-Functional Collaboration: Successfully worked with diverse teams to deliver projects on time, ensuring technical and design requirements are met. Research & Innovation: ● Earthquake Prediction: Contributed to a research project at NESAC focused on predicting earthquakes using multi-parameter analysis. ● SCADA Systems: Gained hands-on experience in SCADA systems and automation during my internship at C-DAC Bangalore. Education & Background: ● B.Tech. in Electronics and Communications Engineering: Graduated with a CGPA of 8.67 from National Institute of Technology, Sikkim. ● Campus Ambassador: Served as a Campus Ambassador for LearnVern and Internshala, enhancing my communication, outreach, and leadership skills. Professional Highlights: ● Published Work: Developed a novel XSI-based die file flow published at DTTC. ● Event Coordination: Successfully coordinated events like the college tech fest "Abhiyantran" and secured sponsorship from Internshala. ●Growth Hacking: Facilitated outreach efforts and onboarded a significant number of students for ePoise. I am passionate about leveraging my technical expertise to drive innovation and efficiency in semiconductor design. My experience spans from leading complex SoC projects to contributing to cutting-edge research initiatives. I am always eager to collaborate with like-minded professionals and contribute to the advancement of technology. Feel free to connect with me to explore opportunities for collaboration or to discuss the latest trends in SoC design and VLSI technology.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Physical Design.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs

Skills

Physical Design Verification
Vlsi Design
Lv/subfc Integration
Physical Design

Career Highlights

Expert in Physical Design Verification and VLSI Design.
Published novel XSI-based die file flow at DTTC.
Led successful integration of SubFCs across multiple projects.

Work Experience

Intel Corporation

SoC Design Engineer (7 yrs 11 mos)

Physical Design Intern (8 mos)

CDAC Bangalore

Intern (2 mos)

Learnvern

Campus Ambassador (1 yr)

North Eastern Space Applications Centre (NESAC)

Research Internship (1 mo)

Internshala

Internshala Student Partner 6.0 (5 mos)

ePoise

Growth Hacker Intern (2 mos)

Education

Bachelor of Technology (B.Tech.) at National Institute Of Technology Sikkim

12th at Sri Chaitanya Vidyaniketan,Visakhapatnam

10th at D.A.V. Public School,Begusarai

Navneet Kishan

Product Engineer

Bengaluru, Karnataka, India8 yrs experience

Highly Stable

Key Highlights

Expert in Physical Design Verification and VLSI Design.
Published novel XSI-based die file flow at DTTC.
Led successful integration of SubFCs across multiple projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Physical Design.

Contact

Skills

Core Skills

Physical Design VerificationVlsi DesignLv/subfc IntegrationPhysical Design

Other Skills

Design Rule Checking (DRC)Layout Versus Schematic (LVS)Layout IntegrationAntennaDie File Creation and EditingTCLRDLNDMQuality checksBrand Ambassador ProgramsSCADAAutomationEntrepreneurshipInterview PreparationNetworking

About

Experience

8 yrs

Total Experience

8 yrs

Average Tenure

8 yrs

Current Experience

Intel corporation

2 roles

SoC Design Engineer

Jun 2018 – Present · 7 yrs 11 mos · Bengaluru, Karnataka, India · On-site

● Led LV Analysis & Cleanup: Successfully resolved DRCs for 12 projects on 7nm, 6nm, 4nm, and 10nm technologies, ensuring timely closure. Trained teams on LV flows for SoC designs.
● SubFC Integration & Management: Coordinated SubFC integration across three projects, managing seven SubFCs for seamless integration and closure.
● Die File Creation & Bump Planning: Developed a novel XSI-based die file flow published at DTTC, ensuring compliance with FC checks for Intel's 4nm and 7nm server products and TSMC designs.
● Streamlined PNR ECOs: Managed and optimized PNR ECO processes for the 4nm server product partitions, meeting technical and design requirements within tight timelines.
● Multi-Technology Expertise & Collaboration: Resolved complex LV/SubFC issues across multiple node technologies while collaborating with cross-functional teams to deliver projects on time.

Design Rule Checking (DRC)Layout Versus Schematic (LVS)Layout IntegrationAntennaDie File Creation and EditingTCL+2

Physical Design Intern

Oct 2017 – Jun 2018 · 8 mos · Bengaluru, Karnataka, India · On-site

● Contributed to RDL routing tasks using Synopsys ICC2, and contributed to
bump placement by creating and editing die files to meet project
requirements.
● Integrated IPs into SoC environments through SHIP, automated workflows
with custom scripts.

Die File Creation and EditingRDLNDMQuality checksPhysical Design

Cdac bangalore

Intern

May 2017 – Jul 2017 · 2 mos · Banglore, India · On-site

● Completed an internship at C-DAC Bangalore, focusing on SCADA (Supervisory Control and Data Acquisition) systems and automation.
● Gained hands-on knowledge of SCADA fundamentals, communication protocols, and security aspects.
● Conducted industrial visits to SRLDC, CPRI, and ABB Pvt. Ltd. to gain practical insights into real-world applications.
This internship provided valuable experience in the field of SCADA and automation, enhancing my technical skills and industry understanding.

SCADAAutomation

Learnvern

Campus Ambassador

Dec 2016 – Dec 2017 · 1 yr · Remote

● Served as a Campus Ambassador for LearnVern, a platform offering free courses in vernacular languages.
● Promoted the platform within my university, encouraging students to leverage the resources for skill development and education.
This role enhanced my communication and outreach skills, allowing me to connect with students and promote educational opportunities.

Brand Ambassador Programs

North eastern space applications centre (nesac)

Research Internship

Dec 2016 – Jan 2017 · 1 mo · Umiam,Meghalaya · On-site

● Contributed to a research project focused on predicting earthquakes using a multi-parameter approach at NESAC.
● Conducted extensive research by analyzing various parameters derived from different geographical indicators to forecast earthquakes.
This project involved in-depth analysis and utilization of diverse data sets to develop predictive models for earthquake forecasting, enhancing my skills in research, data analysis, and geospatial applications.

ResearchGeographic Information Systems (GIS)

Internshala

Internshala Student Partner 6.0

Sep 2016 – Feb 2017 · 5 mos · Remote

● Served as the Campus Ambassador for Internshala at NIT Sikkim.
● Coordinated and conducted events, including our college's Tech Fest "Abhiyantran," on behalf of Internshala.
● Successfully secured sponsorship from Internshala for our college tech fest during my tenure.
● Managed the Facebook page to raise awareness about Internshala's opportunities among my college community.
This role honed my organizational, promotional, and leadership skills, while also enhancing my ability to engage and inform students about valuable internship opportunities.

EntrepreneurshipInterview PreparationNetworking

Epoise

Growth Hacker Intern

Aug 2016 – Oct 2016 · 2 mos · Remote

● Provided suggestions for the enhancement of India's first interview preparation app, ePoise.
● Facilitated outreach efforts by connecting with my contacts within and outside my college to promote the app.
● Coordinated with multiple college ambassadors across various cities to expand the user base and successfully onboarded a significant number of students.
This role involved strategic feedback, effective networking, and collaborative efforts to drive user engagement and growth for the ePoise platform.