Soumabrata Guha

Software Engineer

Bangalore Urban, Karnataka, India4 yrs 4 mos experience
Highly Stable

Key Highlights

  • Expert in UVM and SystemVerilog for IP verification.
  • Proven track record in reducing time-to-market for IP blocks.
  • Strong analytical skills for debugging design issues.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in IP design verification.

Contact

LinkedIn

Skills

Core Skills

Design VerificationUniversal Verification Methodology (uvm)

Other Skills

Assertion and constraints based testcasesCoverage driven testcasesSchematic tracingWaveform tracingAMS verificationRTL DesignVerilog HDLAssertionsConstraintsFunction coverageCode coverageTest PlanningInternet Protocol (IP)AMBA AHBCDC

About

As a dedicated professional in the field of IP Design Verification, I specialize in ensuring that intellectual property cores are meticulously designed, functionally correct, and ready for seamless integration into larger systems. With a strong foundation and 3+ years of experience in digital design and verification methodologies, I bring a detail-oriented approach to validating the performance and reliability of IP components. Key Expertise: Verification Methodologies: Proficient in UVM, SystemVerilog, and other industry-standard verification frameworks. Testbench Development: Skilled in creating robust testbenches to simulate and validate IP functionality under various scenarios. Simulation Tools: Experienced with leading EDA tools such as Cadence Xcelium Synopsys VCS, Verdi and Mentor Graphics Questa. Coverage Analysis: Adept at implementing functional and code coverage techniques to ensure comprehensive verification. Debugging and Problem-Solving: Strong analytical skills to identify and resolve design issues, ensuring high-quality IP delivery. Professional Highlights: Successfully verified multiple IP blocks, leading to reduced time-to-market and enhanced product reliability. Collaborated with cross-functional teams to integrate verified IP into larger SoCs, ensuring seamless functionality. Continuously updated verification environments and methodologies to incorporate the latest industry advancements and best practices. Passion for Excellence: My commitment to excellence drives me to stay at the forefront of technology trends, continuously enhancing my skills and knowledge. I thrive in dynamic environments where innovation and precision are paramount, and I am passionate about contributing to the development of cutting-edge technology. Let's connect if you are interested in discussing the intricacies of IP design verification or exploring opportunities for collaboration in the semiconductor industry.

Experience

4 yrs 4 mos
Total Experience
3 yrs 8 mos
Average Tenure
8 mos
Current Experience

Amd

Silicon Design Engineer 2

Sep 2025 – Present · 8 mos · Bengaluru, Karnataka, India

Globalfoundries

2 roles

Senior Engineer

Jan 2022 – Sep 2025 · 3 yrs 8 mos · Bangalore Urban, Karnataka, India

  • Development of NVMe testcase and test plan for Functional verification of memory IP in UVM environment.
  • Coverage driven testcases.
  • Assertion and constraints based testcases.
  • Closely worked on Schematic tracing and waveform tracing to debug multiple design issues.
  • worked on AMS verification of IP.
  • RTL Design of ADPLL in Verilog HDL. Synthesis of the same design.
Design verificationUniversal Verification Methodology (UVM)Assertion and constraints based testcasesCoverage driven testcasesSchematic tracingWaveform tracing+3

Intern

Jul 2021 – Jan 2022 · 6 mos · Bangalore Urban, Karnataka, India

RTL Design

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI

Jan 2020 – Jan 2022

Maulana Abul Kalam Azad University of Technology, West Bengal formerly WBUT

B.Tech — Electrical Engineering

Jan 2014 – Jan 2018

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