Ronak Bhalodia

Director of Engineering

Bengaluru, Karnataka, India19 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led SoC verification for multiple Intel CPU generations.
Expert in pre-Si functional verification and team leadership.
Pioneered innovative SoC solutions for modern computing.

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in SoC design and validation.

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Skills

Core Skills

SocVerificationIntegration

Other Skills

SoC VerificationPre-Si Functional VerificationTeam LeadershipStrategic PlanningPower ManagementAIMobile ProcessorsGaming PerformanceVerification ManagementCross-site ExecutionCross-site CollaborationUncore IntegrationPCIE SubsystemPCIETest Plan Development

About

At Intel Corporation, our team's dedication to SoC verification for Client PC projects has been a continuous journey of innovation and precision. With a focus on Desktop and Laptop platforms, we've honed skills in pre-si microprocessor architecture verification to ensure each design meets the highest standards. Leading the charge in SoC verification, I've fostered a culture of excellence that prioritizes thorough testing and quality results. The success of our projects is rooted in a collaborative approach, leveraging the collective expertise to deliver SoC solutions that power modern computing. My role has expanded beyond verification to include team leadership and strategic planning, ensuring that Intel's verification processes remain at the forefront of the industry. It's a mission that not only drives technological advancement but also underscores my commitment to elevating our organization's capabilities within the dynamic landscape of semiconductor engineering.

Experience

19 yrs 7 mos

Total Experience

9 yrs 9 mos

Average Tenure

17 yrs 5 mos

Current Experience

Intel corporation

4 roles

Director of Engineering

Promoted

Aug 2022 – Present · 3 yrs 9 mos

Handling SoC Verification team(50+) for Intel Client PC-Desktop/Laptop Projects.
Pre-Si functional verification across IPs/Sub-systems/SoC/FC-Emulation across multiple domains.
Projects/Charter :
Lunarlake(Mx) - 15th Gen Intel Client ultra-low power AI Mobile-PC SoC. Best-in class Power-efficiency with on-chip Memory.
Pantherlake-P/U -Mobile processor family designed for thin-and-light laptops and gaming handhelds, offering up to 70% better gaming performance and higher AI capacity than previous gen. Built on the 18A process,

SoC VerificationPre-Si Functional VerificationTeam LeadershipStrategic PlanningSoCVerification

Sr. Engineering Manager

Apr 2020 – Jul 2022 · 2 yrs 3 mos

Projects/Charter :
RaptorLake (13th Gen) Desktop-S A0/B0 SKUs &
RaptorLake (13th Gen) Laptop-P J0/Q0 SKUs
Verification Manager : Leading SoC Verification execution for RaptorLake Desktop(A0/B0)/Mobile(J0/Q0) SKUs - Intel 13th Gen client CPU product lines: (2020-21, Team – 20+)
Protocol/Domain knowledge : Client Derivative SoC Verification Execution ownership.
TFM : SV-OVM, Saola, Gatekeeper/Pipe mgmt., Synopsis-VCS.
R&R :
SoC Val strategy, TB-infra, Base -> derivative Sync strategy, Milestone definition
SoC Val Milestone definition, Technical reviews & QoV progress tracking & sign-off.
Cross site SoC Val execution across : Uncore / PM/ Performance / DFD / Security & Clocking domains.
SoC PIPE, GK stages, Model Release to FC-Emulation team.
Post-si power-on & platform enabling support.

SoC VerificationVerification ManagementCross-site ExecutionSoCVerification

Engineering Manager

Promoted

Oct 2016 – Mar 2020 · 3 yrs 5 mos

Projects/Charter:
Alderlake (12th Gen) Desktop-S A0/B0 SKUs
Alderlake (12th Gen) Laptop-P (J0/K0) / M (Q0) SKUs
Technical Lead/Manager: Leading SoC Uncore & PM BDC domains verification across
Alderlake (12th Gen) Intel client CPU platforms (2019-20, Team - 15)
Uncore integration & flow verification: PCIE subsystem, Type-C subsystem (TCSS), DMI
SoC Power Management flow verification: PCIE subsystem, Type-C subsystem (TCSS), DMI,
PKG-C & PKG-S states, WR (Warm-reset)
Technical Lead/Manager: PCIE Gen-5/Gen-4 Root-complex based subsystem verification for
Alderlake (12th Gen) Intel client CPU platforms (2019-20, Team - 8)
Icelake (10th Gen) 81r Desktop A0/B0 & G0 SKUs
Technical Lead/Manager: PCIE Gen-4 Root-complex based subsystem verification for Icelake
(10th Gen) Intel client CPU platforms (2017-18, Team - 4)
Protocol/Domain Knowledge: PCIE Gen-4/Gen-5, Type-C, DMI, SOC-PM
TFM: SV-AVM/OVM, Saola, UPF Power-aware simulation, XPROP, Synopsis-VCS.
Roles & Responsibilities:
SS/SoC: Val strategy, TB infrastructure development and ValP definition-reviews
SS release, SoC integration & verification execution
Document and track verification status using coverage matrix and bug tracking system
QoV sign-off: ValP, Regression & Coverage closure

SoC VerificationUncore IntegrationPower ManagementSoCVerification

Sr. Pre-Si Verification Engineer/Lead

Sep 2008 – Sep 2016 · 8 yrs

Handling SoC verification for Client SOC projects. (2015 onwards)
Pre-si Verification owner for Communication and Multimedia specific clusters in INTEL's IA-Atom based Mobile Platforms. (2008-2014)
SoC level verification for HSIC/USB2.0 OTG/SPH clusters in generations of Intel IA-Atom based Mobile Platforms.
SoC level verification for xHCI based USB3.0 cluster for Mobile/Tablet SoCs.
JTAG through USB, IP and SoC Integration Verification for Intel SoC.
Driving Global Validation Activities with SoC Verification team,
HDMI 1.3 (2-D Display) Cluster Verification for Mobile platform.
Activities :-
Verification Test plan development.
Developing OVM based Verification environment at SoC level. Integrating 3rd party VIP in to SoC-OVM validation environment.
Coding Modular, Reusable & Configurable Sequences/Tests.
Coding Functional coverage, SV-Assertions.
Working with Emulation team on enabling cluster verification on FPGA and providing debug support.
Working with System validation team to provide sighting debug support for post silicon validation.
Working with Platform team for debugging Driver/SW related opens and debugging end-costumer issues.
Guiding/Ramping up Juniors/CWs on cluster verification.
Tools: VCS-mx (Synopsis), Nova’s Verdi.
Languages/Methodologies: System Verilog, OVM, AVM.
Standards: - USB3.0, SSIC, PIPE protocols. Fundamentals of xHCI, JTAG through USB
USB 2.0, UTMI, ULPI, HSIC, OTG protocols. EHCI.
AMBA AXI/AHB/APB, OCP 2.0, HDMI 1.3 Protocols.

SoC VerificationTest Plan DevelopmentIntegration VerificationSoCVerification

Conexant

Sr. Design & Verification Engineer

Jul 2006 – Sep 2008 · 2 yrs 2 mos · Pune/Pimpri-Chinchwad Area

Sr. Design & Verification Engineer, PLATFORM IP Group.
USB2.0 IP and SoC integration verification.
As a part of IP design and verification group, responsible to handle USB IP level & SoC integration Verification, which is essential digital IP block in CONEXANT’s various ARM based broadband access, wireless LAN and broadband media processing group’s SoCs. USB IP core consist of USB 2.0 High Speed OTG controller that supports UTMI, ULPI and USB 1.1 legacy mode using the same hardware. It supports AMBA-AHB compliant system bus interface.
Activities:
Preparing test-plan and writing testcases in Verilog and C for chip (system) level verification.
Running unit level and system level regressions, GLS for USB cluster.
Top level architectural (wrapper) design of digital USB subsystem in verilog,
Removing CDC and synthesis related errors from RTL through Spyglass analysis. Code coverage analysis, Chip (system) level IP integration in various SoCs,
Debugging issues with FPGA team while mapping new USB core RTL on FPGA.
Projects: Centaur, Gryphon (DSL) and Xenon3 (PON) SoCs from Broadband Access group.
Talia and VirgoUltra SoCs from Broadband Media Processing group.
Tools: Incisive NC-verilog, NC simvision, ICTR for code coverage, Spyglass, Nova’s Verdi.
Languages: Verilog, C, Perl.
Standards: USB 2.0, UTMI, ULPI, OTG, USB 1.1, AMBA AHB/APB protocols.
AHB-PCI Bridge IP & SoC integration verification.
The PCI-AHB bridge interface enables interfacing any chip to industry-standard PCI peripherals via a 32-bit multiplexed address/data bus.
Activities:
Writing test cases in C and Verilog for unit level verification, running Regression.
Analyzing code coverage using Cadence’s ICTR tool for IP.
Projects: GallusWB chip from Broadband Access group.
Standards: AMBA AHB/APB protocol, Basic of PCI bus protocol.
Tools: Incisive NC-Verilog, NC simvision, ICTR for code coverage.
Languages: Verilog, C, Perl.

USB IntegrationVerificationTest Case DevelopmentIntegration

Motorola, bangalore

Trainee Engineer, DSP Group

Jan 2006 – Jun 2006 · 5 mos

M.Tech final semester internship at DSP group,MOTOROLA Bangalore.
Worked on “Efficient Bit-allocation technique for MPEG Advance Audio Coder” Aim was to improve quality of the AAC coder by applying concept of Perceptual Entropy for efficient Bit-allocation technique.
This project requires base knowledge of Psychoacoustics of audio & bit allocation algorithms. Developed Algorithm using C and Matlab 6.1 in UNIX, Solaris environment.