RAJESH R

Software Engineer

Bengaluru, Karnataka, India6 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Senior Design Verification Engineer with extensive SoC expertise.
  • Proficient in SystemVerilog and UVM methodologies.
  • Strong background in C programming for design verification.
Stackforce AI infers this person is a Design Verification Engineer specializing in semiconductor and hardware verification.

Contact

LinkedIn

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)C

Other Skills

System on a Chip (SoC)Verilog

Experience

6 yrs 7 mos
Total Experience
2 yrs 2 mos
Average Tenure
2 yrs 2 mos
Current Experience

Amd

Senior Design Verification Engineer

Mar 2024 – Present · 2 yrs 2 mos · Penang, Malaysia · On-site

SystemVerilogUniversal Verification Methodology (UVM)

Maxlinear

Engineer

Feb 2023 – Dec 2023 · 10 mos · Bengaluru, Karnataka, India · On-site

CSystemVerilog

Frenustech pvt ltd

Asic Design verification Engineer

Jul 2019 – Feb 2023 · 3 yrs 7 mos · Bengaluru, Karnataka, India

Education

The national institute of engineering mysore

Bachelor of Engineering — Electronics and Communications Engineering

Jan 2013 – Jan 2017

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