Anjaneyulu Chette

Software Engineer

Bengaluru, Karnataka, India7 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL Verification and UVM methodologies.
  • Proficient in debugging and developing testbenches.
  • Strong background in ASIC design and verification.
Stackforce AI infers this person is a Design Verification Engineer specializing in ASIC and RTL methodologies.

Contact

LinkedIn

Skills

Core Skills

Rtl VerificationUniversal Verification Methodology (uvm)

Other Skills

PCIeSystem verilogAssertion Based VerificationFunctional and Code coverageAMBA Protocols AHBAPBAXIDebuggingEDAApplication-Specific Integrated Circuits (ASIC)RTL CodingVerilogMentor Graphics Quastasim

Experience

7 yrs 9 mos
Total Experience
2 yrs 6 mos
Average Tenure
4 yrs 5 mos
Current Experience

Amd

Design Verification Engineer

Dec 2021 – Present · 4 yrs 5 mos · Hyderabad, Telangana, India

PCIeSystem verilogUniversal Verification Methodology (UVM)Assertion Based VerificationFunctional and Code coverageAMBA Protocols AHB+9

Tessolve

DV Engineer

Nov 2019 – Nov 2021 · 2 yrs · Bengaluru, Karnataka, India

Digicomm semiconductor private limited

Design Verification Engineer

Jul 2018 – Oct 2019 · 1 yr 3 mos · Bengaluru, Karnataka, India

  • Including internship

Education

Guru Nanak Institute Of Technical Campus Hyderabad (JNTU)

Bachelor of Technology - BTech

Govt.Institute of Electrons(GIOE) Secunderabad

Diploma in Electronics and Communications

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