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Ashok Kumar Kuna

Software Engineer

Bengaluru, Karnataka, India10 yrs 5 mos experience

Key Highlights

Expert in Mixed-Signal IC Design and Analog Circuit Design.
Proven experience with USB2 and UCIe Protocols.
Strong background in chip design across multiple process nodes.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Mixed-Signal and Analog Circuit Design.

Contact

Skills

Core Skills

Mixed-signal Ic DesignAnalog Integrated Circuit Design

Other Skills

Design Team CoordinationMixed-Signal Integrated CircuitsCadence VirtuosoAnalog Circuit DesignH-SpiceVerilogMatlab

About

Keen to work with strong technical teams in SERDES Domain. I have worked in DPHY, UCIe A, Chip to Chip (16 GT/s), USB2 , Type-C Power Delivery (TCPD) Protocols and common blocks such as Bandgap, LDO, Resistor Calibration, SAR ADCs.

Experience

10 yrs 5 mos

Total Experience

2 yrs

Average Tenure

3 mos

Current Experience

Amd

MTS Silicon Design Engineer

Feb 2026 – Present · 3 mos · Bangalore Urban, Karnataka, India · Hybrid

Chipex technologies

Analog Design Lead

Jun 2024 – Jan 2026 · 1 yr 7 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

Senior Analog Design Engineer

May 2022 – Jun 2024 · 2 yrs 1 mo · Bengaluru, Karnataka, India · On-site

Worked on chip to chip and UCIe Protocol, complete link sims for systems margin. Each Lane top speed is 16 GT/s.
Worked on Intel 16 nm and Intel 3 nm process nodes

Design Team CoordinationMixed-Signal IC Design

Cadence design systems

2 roles

Lead Analog Design Engineer

Promoted

Jul 2019 – Apr 2022 · 2 yrs 9 mos

Presently working on Full Speed Transmitter of USB2 Protocol and Worked on Current Mode Bandgap Circuit with Calibration Circuitry.

Mixed-Signal IC DesignMixed-Signal Integrated Circuits

Analog Design Engineer

Jul 2017 – Jun 2019 · 1 yr 11 mos

Worked on BG, Squelch and Disconnect blocks in USB2 Protocol.
Worked on TypC power delivery Blocks in TypC protocols.
Worked in 28FDSOI, t7g, ss7lpp and t5gp process nodes.

Analog Integrated Circuit DesignCadence VirtuosoAnalog Circuit Design

Intel corporation

Analog Intern

Jan 2017 – Jun 2017 · 5 mos · Bangalore, India

Designing and testing of 0.9V Low Dropout(LDO) Regulators

Birla institute of technology and science, pilani

Teaching Assistant

Aug 2015 – Dec 2016 · 1 yr 4 mos · Pilani

Worked as teaching assistant to help B.E students in their academic projects.

Education

Birla Institute of Technology and Science, Pilani

ME — Micro Electronics

Jan 2015 – Jan 2017

RGUKT-Basar

Bachelor's Degree — Electronics and communication Engineering

Jan 2008 – Jan 2014

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