Ayush Agarwal — Product Engineer

Passionate design for testability engineer. Currently working as DFT RTL Implementation engineer at Nvidia. Implementating mentors SSN scan architecture for Nvidia GPUs/SOCs Have knowledge of EDT/SSH architecture to implement SSN at RTL level. Below work is done during M.tech at ITGN: Worked on radiation-hardened memories(latches and SRAM). Proposed three new radiation-hardened robust latches that can tolerate multi-node upset with minimum delay and area overhead. (preparing manuscript for a journal paper - TCAS-1). Done RTL to GDS of 2 stages pipelined processor. (Knowledge of ASIC flow) Good knowledge of Verilog and done verification of different RTL codes using Xilinx Vivado. Performed scan chain insertion and ATPG in multiple blocks using Tessent(DFT). Designed Layout of mirror adder, guard gate, Write driver, and precharge circuit for SRAM and performed DRC, LVS, and PEX on the same using Cadence Virtuoso. passionate about yoga, fitness, food, travel, and spirituality Tools: Synopsys VCS, Xilinx Vivado, Cadence Virtuoso, Mentor Tessent, Innovus, Calibre. Technical skills: Verilog, cadence skill scripting, Basic C and python Courses: VLSI Design, Physics of transistors, Microelectronics lab, Analog CMOS IC design, Micro-fabrication

Stackforce AI infers this person is a VLSI Design Engineer with expertise in DFT and RTL methodologies.

Location: Agra, Uttar Pradesh, India

Experience: 4 yrs 10 mos