Pradeep Reddy

Software Engineer

Hyderabad, Telangana, India9 yrs 11 mos experience

Key Highlights

  • Experienced in DFT engineering and ASIC design.
  • Proficient in Verilog and System Verilog.
  • Strong background in silicon design and engineering.
Stackforce AI infers this person is a DFT Engineer with expertise in ASIC design and silicon engineering.

Contact

LinkedIn

Skills

Other Skills

verilogSystem verilogPerlC++C

Experience

9 yrs 11 mos
Total Experience
2 yrs 10 mos
Average Tenure
1 yr 3 mos
Current Experience

Cadence

Principal Design Engineer

Feb 2025 – Present · 1 yr 3 mos · On-site

Stealth startup

Staff Asic Design Engineer

Jun 2024 – Feb 2025 · 8 mos

Amd

Sr Silicon Design Engineer

Aug 2021 – May 2024 · 2 yrs 9 mos

Soctronics

4 roles

Senior Design Engineer

Sep 2020 – Jul 2021 · 10 mos

Design Engineer - 2

Promoted

Apr 2018 – Aug 2020 · 2 yrs 4 mos

Design Engineer - 1

Feb 2017 – Mar 2018 · 1 yr 1 mo

Engineer Trainee

Jan 2016 – Jan 2017 · 1 yr

Education

JNTU Anantapur

Audisankara College of Engineering & Technology, Gudur

Bachelor of Engineering - Btech

Jan 2010 – Jan 2014

Narayana Junior college

mpc — MPC

Jan 2007 – Jan 2009

Sri Vivekananda High School

SSC

Jan 2006 – Jan 2007

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