S

Satya Gupta

CEO

Noida, Uttar Pradesh, India24 yrs 11 mos experience
Highly Stable

Key Highlights

  • 24+ years of experience in SOC design and development.
  • Expert in leading multi-site, multi-cultural teams.
  • Proficient in low power design and quality checks.
Stackforce AI infers this person is a semiconductor design expert with extensive experience in SoC development and team management.

Contact

Skills

Core Skills

SocLow-power Design

Other Skills

Static Timing AnalysisFormal VerificationRTL DesignDebuggingASICSOC IntegrationLogic SynthesisApplication-Specific Integrated Circuits (ASIC)SemiconductorsVery-Large-Scale Integration (VLSI)EDAEmbedded SystemsSystem on a Chip (SoC)

About

24+ years of experience in SOC design and development, with the successful execution of numerous complex SoCs in Consumer, Automotive and Compute domains. Currently working as a SOC design manager. Responsible for SOC FE design including SOC RTL, netlist, constraints, Low power design, CDC, RDC and other quality checks. The role involves leading and executing with a large team of people across domains ranging from Specs Definition with Product Management & Architecture teams, IP schedule and feature stagging with IP teams, Design execution with Design, DV, Emulation, Synth, DFT, STA & PD teams. Hands-on experience in SOC design and implementation activities starting from specs, RTL design, SOC integration, Synthesis, Formal verification, Timing Signoff, Low power design, CDC checks, CTS specs, IP procurement, Interconnect restructuring, Functional and Timing ECOs. Having a good understanding of Physical design and implementation. Responsible for people management, defining annual objectives, performance assessment, team skill set development, resource allocation and tracking, initiatives for flow/methodology development or enhancement, and deployment of new methodologies to enhance productivity. Experienced in leading and working in a multi-site, multi-cultural and interdisciplinary environment focusing on attaining the best device PPA.

Experience

24 yrs 11 mos
Total Experience
4 yrs 2 mos
Average Tenure
3 yrs 8 mos
Current Experience

Amd

Sr. Manager at AMD

Sep 2022Present · 3 yrs 8 mos · Bengaluru, Karnataka, India

SoCStatic Timing AnalysisLow-power DesignFormal VerificationRTL DesignDebugging+9

Mediatek

Sr Manager

Sep 2021Sep 2022 · 1 yr · Bengaluru, Karnataka, India

Cadence design systems (india) pvt. ltd.

Senior Principal Engineer

Feb 2019Sep 2021 · 2 yrs 7 mos · Noida, Uttar Pradesh, India

Nxp semiconductors

Principal Engineer

Jun 2017Feb 2019 · 1 yr 8 mos · Noida Area, India

  • SOC Design Lead

St microelectronics

2 roles

Sr. Manager

Promoted

Sep 2012Jun 2017 · 4 yrs 9 mos · Noida, Uttar Pradesh, India

  • SOC FE design and implementation lead.

Engineering Specialist

Nov 2000Jan 2012 · 11 yrs 2 mos · NOIDA

Education

Indian Institute of Technology, Kharagpur

M.Tech.

Jan 1999Jan 2001

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