Harsh Gupta

Director of Engineering

Bengaluru, Karnataka, India26 yrs 4 mos experience

Highly Stable

Key Highlights

25 years of experience in SoC and IP verification.
Expert in SystemVerilog and UVM methodologies.
Proven track record in improving SoC verification quality.

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in SoC and IP verification methodologies.

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Skills

Other Skills

DebuggingSemiconductorsEDAEmbedded SystemsSimulationsOpen Verification MethodologyEmbedded SoftwareVHDLApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)

About

Expertise in SOC & IP verification using HVL (SystemVerilog, e and using methodologies) in area of Mobile Application Processor, Medical Electronics, TV & Broadcasting, Networking/Telecom ASICs, Printers SoC, Digital TV SoCs and Server Chipsets. Expertise in the HVL (SystemVerilog) and Methodologies like UVM and OVM. Good experience in embedded systems (embedded software, board & system design) gives an added advantage and strenghten my skills in SoC Design Verification. Approximately 25 years of experience in engineering deliveries for simulation tools, SoC and IP for various domain and product lines. In era of convergance and ever shrinking Time-To-Market window, I want to utilize my HW & SW skills to improve quality and productivity of SoC verification to get first time right silicon always. Specialties: - SystemVerilog, e, Methodologies (OVM, UVM, eRM) - SoC Verification, Co-simulations, Architecture Exploration & Behavioural Modelling

Experience

26 yrs 4 mos

Total Experience

3 yrs 3 mos

Average Tenure

2 yrs 3 mos

Current Experience

Synopsys inc

2 roles

Director SOC Engineering

Promoted

May 2026 – Present · 0 mo

Senior Manager SOC Engineering

Jan 2024 – Apr 2026 · 2 yrs 3 mos

Amd

Senior Design Manager at AMD

Feb 2022 – Dec 2023 · 1 yr 10 mos · Hyderabad, Telangana, India

Xilinx

Senior Engineering Manager

Dec 2016 – Feb 2022 · 5 yrs 2 mos · Hyderabad, Telangana, India

Managing a Verification team to deliver next Gen Xilinx FPGA's on 7nm technology node.
Providing technical guidance and mentoring the team to come up new advanced flows and methodologies to enhance quality, increase automation and to reduce the verification time.

Rambus

Principal Engineer

Sep 2016 – Dec 2016 · 3 mos · Bengaluru Area, India

Worked on the SoC(for server backplane connectivity) level verification

Semtech

Senior Staff Verification Engineer

Jan 2014 – Aug 2016 · 2 yrs 7 mos · Bhubaneshwar Area, India

Working on the creation of the System level verification environment of SoC's right from defining the architecture of testbench, coverage goals to verification and coverage closure. Worked on chips for IoT applications (baseband), Gearbox for UHD-SDI. Extensively worked on creating UVM environments and UVC creations for the verification of these chips.

Cadence design systems

2 roles

Member of Consulting Staff

Promoted

Jul 2010 – Dec 2013 · 3 yrs 5 mos · Noida Area, India

Leading the team of engineers to validation of the methodologies like UVM in the Simulator. Also responsible to create UVM and SystemVerilog based test-benches for the SoC subsystem.

Senior Member of Technical Staff

May 2005 – Jun 2010 · 5 yrs 1 mo · Noida Area, India

Lead a team of 5 engineers to :
Handle the tasks of validating latest verification methodologies and techniques (like UVM and SystemVerilog) at the level of ARM-A9 based SoC subsystems.
Responsible for identifying, implementing and tracking test and code coverage against product features and test plans for ARM-A9 based SoC subsystems
Perform responsibilities of developing random, critical, and application level tests to ensure full feature coverage
Assigned the tasks of implementing verification methodologies like traffic generators and interface protocol checkers
Perform verification of functional coverage by applying System Verilog assertions and writing cover groups.
Development of VIP’s, UVC’s and reactive test benches.