vijaysai kancharla — Software Engineer

> Having over 8 years of experience in VLSI involving timing closure, timing correlation, years of experience as PD & STA Engineer. > Worked on Full chip coverage and Full chip sign off. > Experience in DRV, Noise, Timing & Annotation analysis on Prime Time. > Proficient in writing the timing ECO’s and providing timing budgets for interface blocks. > Proficient in validating constraints b/w MSOC & Block level > Developed scripts for collaterals update, Providing budgets for interface blocks. > Experience in PNR of blocks (like Synthesis, Floor planning, placement, CTS, route &signoff) & individual contributor. > Executed the block from Netlist to GDSII and perform block-level sign-off checks. > Familiarity with TCL and UNIX work history. >Having hands-on exposure to tools like Genus, Innovus, Tempus, Design Compiler, IC Compiler, Primetime, Aprisa, Redhawk, Conformal Low Power, Conformal LEC and Calibre. > Worked as an individual contributor in various evaluations for PPA push and project executions. >Well acquainted with solving a wide array of problems including but not limited to timing closure, congestion mitigation, area and power reduction. > Well versed with UNIX and TCL scripting. - Can work effectively alone and as a team member.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in physical design and timing analysis.

Location: Andhra Pradesh, India

Experience: 9 yrs 2 mos