Kaustubh Apte

Software Engineer

Bengaluru, Karnataka, India12 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and Static Timing Analysis
Proficient in EDA tools for advanced semiconductor technologies
Developed innovative scripts to enhance design efficiency

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Power and Signal IntegrityPerlTCLEDA ToolsSynopsys PrimetimeRedhawk IR drop analysisVLSIDigital ElectronicsMatlabDigital Signal ProcessingDigital Circuit DesignTransformer

Experience

12 yrs

Total Experience

4 yrs

Average Tenure

4 yrs

Current Experience

Sima.ai

2 roles

Member of Technical Staff

Jan 2024 – Present · 2 yrs 5 mos · Bengaluru, Karnataka, India

Sr Staff

Jun 2022 – Jan 2024 · 1 yr 7 mos · Bengaluru, Karnataka, India

Intel corporation

SoC Design Engineer

May 2017 – Jun 2022 · 5 yrs 1 mo · India

Qualcomm

2 roles

Engineer, Associate

Jun 2014 – May 2017 · 2 yrs 11 mos · Bengaluru Area, India

As a part of Physical Design team, I have implemented various hard-macros and tiles from netlist to gds on latest technologies (finFETs, merged N-well) and latest process nodes (16nm, 14nm, 10nm) achieving the power, area and performance targets.
My role includes- partitioning, floorplanning, constraints correlation checks, UPF based PnR, Raw-clock and clock-tree analysis, power and signal integrity, logic and low-power equivalence check, timing closure/ECO generation, physical verification- LVS, DRC. DP and others.
I have got good exposure on EDA tools- Olmypus, ICC, Innovous (for floorplanning), Primetime, Redhawk (for power and signal integrity), Calibre (gds signoff).
I am also proficient at perl and tcl scripting and have automated many manual tasks in the routine work.

Physical DesignStatic Timing AnalysisPower and Signal IntegrityPerlTCLEDA Tools

Interim Engineering Intern

May 2013 – Jul 2013 · 2 mos · Bangalore

Worked in Static Timing Analysis methodology team.
Tool- Primetime
Scripting language- Perl , Tcl
Developed "Hold Violation Analyzer" script using perl and tcl. Some of the featrures are- multi-mode, multi-corner analysis, suggesting optimum fixes considering bottleneck points, setup margin slack, clock-skew and various other parameters, xls output which PD engineer can easily filter based on desired parameters. Got "Qualstar" for this work.

Static Timing AnalysisPerlTCL

Siemens india p ltd.

Summer Intern

Jun 2012 – Jul 2012 · 1 mo · mumbai

Siemens is SCADA (Supervisory Control And Data Acquisition) vendor for Maharashtra State Electricity Transmission and Distribution Company (MSETCL and MSEDCL). As a part of internship, I worked with the project team to understand the deployment of SCADA network in the field and visited substation where the live data for the region was being captured.
Prepared a report with hands on experience under the guidance of Siemens officials. It includes- necessity of automation in the power sector; architecture of SCADA system implemented by Simenes; RTU and FRTU architecture and their operation; communication network setup; time synchronisation; centrallised monitoring of the power transmission grid spread all over the state from the control centre; substation architecture and automation.