Vinay Kumar V

Software Engineer

Bengaluru, Karnataka, India15 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 13 years of experience in power estimation and optimization.
Expertise in low power verification from RTL to netlist.
Proficient in EDA tool development for build flow.

Stackforce AI infers this person is a Low Power Design Architect with extensive experience in semiconductor design and verification.

Contact

Skills

Core Skills

Power VerificationPower EstimationDesign Compiler

Other Skills

upf generationpower estimation flowsquality improvementenhancementcC++Embedded Csystem verilogVerilogvhdlperllow powerupf and cpfVCSLeda

About

Have 13+ years Experience in CPU and SoC Power estimation, analysis,optimization, Low Power verification from RTL to netlist (FCL) and EDA tool development for build flow.

Experience

15 yrs 8 mos

Total Experience

5 yrs 2 mos

Average Tenure

10 yrs 2 mos

Current Experience

Intel corporation

soc design engineer

Apr 2016 – Present · 10 yrs 1 mo · Bangalore

Amd

Senior Design Engineer

Oct 2012 – Mar 2016 · 3 yrs 5 mos · Greater Hyderabad Area

Working on Global build flow for front end verification in Methodology team.
Working on power verification, upf generation in IPs/SoCs and Power estimation flows in Methodology team.

power verificationupf generationpower estimation flowspower estimation