Praveen Sakrappanavar — Software Engineer

• Test plan understanding for DFT. • Good understanding and experience in DFT Scan insertion for Flat and hierarchical designs which involves multiple power domains. • Good experience and understanding in MBIST insertion and simulation at core level and top level. • Good understanding of ATPG at core level and top level. Coverage analysis and improvement. • ATPG pattern generation (power aware & non-power aware) for SAF, TDF and Bridging Faults. Simulation with timing and no-timing. • Good understanding on JTAG & Boundary Scan • Detailed understanding of different type of compression techniques. • Good knowledge on Tcl and Perl scripting. • Have exposure on basic STA checks with PrimeTime. • Basic understanding of Synthesis flow. • Worked closely with STA, EMIR & PD teams. • Worked closely with Test engineers to bring up first silicon. • Silicon bring-up and post silicon debug. • Vmin Analysis and Yield improvement. EDA Tools Knowledge: DFT Compiler, DFT Advisor, Tessent ATPG, TetraMax ATPG, Design Compiler, SpyGlass DFT, LVMBIST, TMBIST, VCS, NCSim, Formality, PrimeTime, VTran

Stackforce AI infers this person is a DFT Engineer with expertise in semiconductor design and testing.

Location: Bengaluru, Karnataka, India

Experience: 12 yrs 2 mos